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| author | Alec Berg <alecaberg@chromium.org> | 2014-09-19 13:48:56 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-24 23:28:07 +0000 |
| commit | 5e7c09ed3eafd548723b58fe108ef5a777158a8d (patch) | |
| tree | d626b0306743017100ab1aa8990c25460e0f8739 /chip/stm32/clock-stm32f0.c | |
| parent | 9bebf41d169d3cac003972a78c4ba46fdd60687c (diff) | |
| download | chrome-ec-5e7c09ed3eafd548723b58fe108ef5a777158a8d.tar.gz | |
stm32f0: samus_pd: add hibernate and enable wake pins for samus
Add hibernate functionality for stm32f0, and enable wake pins
for samus PD MCU. Samus wake pins are VBUS present on either port.
BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto samus PD. test hibernate console command:
> hibernate 0 500000
Hibernating for 0.500000 s
(5 seconds later)
--- UART initialized after reboot ---
[Reset cause: hibernate]
...
> hibernate
Hibernating until wake pin asserted.
(plug in AC)
--- UART initialized after reboot ---
[Reset cause: hibernate]
Change-Id: Ib86f2677721df29e7bf6975e239de79c25a38795
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219105
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 99ef0b2681..bcb72fa070 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -258,6 +258,30 @@ static void config_hispeed_clock(void) #endif } +void __enter_hibernate(uint32_t seconds, uint32_t microseconds) +{ + uint32_t rtc, rtcss; + + if (seconds || microseconds) + set_rtc_alarm(seconds, microseconds, &rtc, &rtcss); + + /* interrupts off now */ + asm volatile("cpsid i"); + +#ifdef CONFIG_HIBERNATE_WAKEUP_PINS + /* enable the wake up pins */ + STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS; +#endif + STM32_PWR_CR |= 0xe; + CPU_SCB_SYSCTRL |= 0x4; + /* go to Standby mode */ + asm("wfi"); + + /* we should never reach that point */ + while (1) + ; +} + #ifdef CONFIG_LOW_POWER_IDLE void clock_refresh_console_in_use(void) |