diff options
| author | Alec Berg <alecaberg@chromium.org> | 2015-05-18 10:57:21 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-27 19:40:18 +0000 |
| commit | 488f8c95651ad85edffff76af410a0fa85433242 (patch) | |
| tree | 53ab05003ff3772a51910b46b06b9c0663000c46 /chip/stm32/clock-stm32f0.c | |
| parent | 97934e4041040997bce215103b67e227aa806732 (diff) | |
| download | chrome-ec-488f8c95651ad85edffff76af410a0fa85433242.tar.gz | |
oak_pd: add initial support for oak PD
Add initial support for Oak PD MCU on rev1 boards.
This does not include USB PD communication.
BUG=none
BRANCH=none
TEST=build and load on oak and get console. test we
resond to host commands from EC using "pdcmd 0 0" on
EC console.
Change-Id: I92045cf0fd682279ada6c286f5399f0e258a6305
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271828
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 3586b64a5c..8940577f94 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -46,6 +46,8 @@ static int dsleep_recovery_margin_us = 1000000; */ #ifdef CHIP_VARIANT_STM32F373 #define STOP_MODE_LATENCY 500 /* us */ +#elif defined(CHIP_VARIANT_STM32F05X) +#define STOP_MODE_LATENCY 300 /* us */ #elif (CPU_CLOCK == PLL_CLOCK) #define STOP_MODE_LATENCY 300 /* us */ #else @@ -245,6 +247,45 @@ static void config_hispeed_clock(void) /* Wait until the PLL is the clock source */ while ((STM32_RCC_CFGR & 0xc) != 0x8) ; +#elif defined(CHIP_VARIANT_STM32F05X) + /* If PLL is the clock source, PLL has already been set up. */ + if ((STM32_RCC_CFGR & 0xc) == 0x8) + return; + + /* Ensure that HSI is ON */ + if (!(STM32_RCC_CR & (1<<1))) { + /* Enable HSI */ + STM32_RCC_CR |= (1<<0); + /* Wait for HSI to be ready */ + while (!(STM32_RCC_CR & (1<<1))) + ; + } + + /* + * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz + * therefore PCLK = FCLK = SYSCLK = 48MHz + */ + /* Switch the PLL source to HSI/2 */ + STM32_RCC_CFGR &= ~(0x00018000); + + /* + * Specify HSI/2 clock as input clock to PLL and set PLL (*12). + */ + STM32_RCC_CFGR |= 0x00280000; + + /* Enable the PLL. */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until PLL is ready. */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL. */ + STM32_RCC_CFGR |= 0x2; + + /* wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; #else /* Ensure that HSI48 is ON */ if (!(STM32_RCC_CR2 & (1 << 17))) { |