diff options
| author | Philip Chen <philipchen@google.com> | 2017-09-22 14:29:40 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-11 13:19:33 -0700 |
| commit | 982f2bbfab02400cb09b7d7102db3285c1723762 (patch) | |
| tree | 1d7e9b38c83b7a54710c61028df3dcaf70a5791d /chip/stm32/clock-stm32f0.c | |
| parent | df12bc1c0246ceec39f28151efadb73f8e5fd7a5 (diff) | |
| download | chrome-ec-982f2bbfab02400cb09b7d7102db3285c1723762.tar.gz | |
chip/stm32/clock: Optionally use LSE as RTCCLK
The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz.
To use stm32 RTC for applications requiring accurate timing, let's setup
LSE (a more accurate clock source) as RTCCLK.
Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally.
BUG=b:63908519
BRANCH=none
TEST=boot scarlet rev1 and wait for an hour,
confirm rtc time == kernel system time.
Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/679601
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index b7eb68ca07..fe1ccd4aa4 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -59,26 +59,27 @@ static int dsleep_recovery_margin_us = 1000000; #endif /* CONFIG_LOW_POWER_IDLE */ /* - * RTC clock frequency (connected to LSI clock) + * RTC clock frequency (By default connected to LSI clock) * - * TODO(crosbug.com/p/12281): Calibrate LSI frequency on a per-chip basis. The - * LSI on any given chip can be between 30 kHz to 60 kHz. Without calibration, - * LSI frequency may be off by as much as 50%. Fortunately, we don't do any - * high-precision delays based solely on LSI. - */ -/* - * Set synchronous clock freq to LSI/2 (20kHz) to maximize subsecond - * resolution. Set asynchronous clock to 1 Hz. + * The LSI on any given chip can be between 30 kHz to 60 kHz. + * Without calibration, LSI frequency may be off by as much as 50%. + * + * Set synchronous clock freq to (RTC clock source / 2) to maximize + * subsecond resolution. Set asynchronous clock to 1 Hz. */ -#define RTC_FREQ (40000 / 2) /* Hz */ + +#ifdef CONFIG_STM32_CLOCK_LSE +#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */ +#else /* LSI clock, 40kHz-ish */ +#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */ +#endif #define RTC_PREDIV_S (RTC_FREQ - 1) #define RTC_PREDIV_A 1 #define US_PER_RTC_TICK (1000000 / RTC_FREQ) - int32_t rtcss_to_us(uint32_t rtcss) { - return ((RTC_PREDIV_S - rtcss) * US_PER_RTC_TICK); + return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_PER_RTC_TICK); } uint32_t us_to_rtcss(int32_t us) @@ -86,7 +87,6 @@ uint32_t us_to_rtcss(int32_t us) return (RTC_PREDIV_S - (us / US_PER_RTC_TICK)); } - void config_hispeed_clock(void) { #ifdef CHIP_FAMILY_STM32F3 |