diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-12-10 14:09:27 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-12-11 17:03:22 -0800 |
| commit | 3a1b5d5acbfa2dada627dd941fead509e6b3a7f6 (patch) | |
| tree | 0b4f42903e5710036e4292330ecbc58d54584711 /chip/stm32/clock-stm32f0.c | |
| parent | 0ad9bd623cd825bf21537edb150a3266e002f5be (diff) | |
| download | chrome-ec-3a1b5d5acbfa2dada627dd941fead509e6b3a7f6.tar.gz | |
stm32: Don't use HSI48 clock for chips which don't support it
stm32f03x and stm32f070 officially do not support an HSI48 clock, so
configure our 48MHz clock using HSI8 and PLL.
BUG=chromium:568717
BRANCH=None
TEST=Verify snoball 1us timer is accurate and we can execute
approximately 48 million NOPs in a second.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347
Reviewed-on: https://chromium-review.googlesource.com/317459
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 8940577f94..a6d297bcb7 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -247,7 +247,10 @@ static void config_hispeed_clock(void) /* Wait until the PLL is the clock source */ while ((STM32_RCC_CFGR & 0xc) != 0x8) ; -#elif defined(CHIP_VARIANT_STM32F05X) +/* F03X and F05X and F070 don't have HSI48 */ +#elif defined(CHIP_VARIANT_STM32F03X) || \ +defined(CHIP_VARIANT_STM32F05X) || \ +defined(CHIP_VARIANT_STM32F070) /* If PLL is the clock source, PLL has already been set up. */ if ((STM32_RCC_CFGR & 0xc) == 0x8) return; |