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| author | Jes B. Klinke <jbk@chromium.org> | 2021-08-30 14:52:26 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-08 18:57:36 +0000 |
| commit | f2af0a3a74192876fc1b72706813d756393da167 (patch) | |
| tree | a53007357e2be115dab1aace09365a4845e109af /chip/stm32/clock-stm32f0.c | |
| parent | f351c02b70c6a7d2137d3770e11e7c3a3850a1c8 (diff) | |
| download | chrome-ec-f2af0a3a74192876fc1b72706813d756393da167.tar.gz | |
chip/stm32: Factor family specific clock logic out of usb.c
The register for enabling USB register clock appears to have been
identical across F0, F3, and G4 families, but for L5 it is
different. Rather than having #ifdef in usb.c (as I recently
committed), this CL will move the clock logic into
clock_enable_module() where it arguably belonged all the time.
Additionally: Some of the chip families make use of a clock_mask in
their implementation of clock_enable_module(), but since the module_id
enum has more than 32 value, until now, some values (among those
MODULE_USB) would result in overflow, causing new_mask to be identical
to clock_mask, and the USB case could have never been reached.
BUG=b:192262089
TEST=Compile servo_v4 without linker errors
BRANCH=none
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 8cfbaef111..0f63bdd394 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -407,9 +407,23 @@ void clock_enable_module(enum module_id module, int enable) else STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN; return; + } else if (module == MODULE_USB) { + if (enable) + STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; + else + STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; } } +int clock_is_module_enabled(enum module_id module) +{ + if (module == MODULE_ADC) + return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN); + else if (module == MODULE_USB) + return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB); + return 0; +} + void rtc_init(void) { rtc_unlock_regs(); |