diff options
| author | Scott Collyer <scollyer@google.com> | 2020-06-17 20:22:56 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-04 21:18:11 +0000 |
| commit | 22c4439064728d0d83e708724c3f3da5fd5e65b3 (patch) | |
| tree | 38c8471d10351e36e0be7238d315412017c01297 /chip/stm32/clock-stm32g4.c | |
| parent | 5906ecf9d006259ed51afddc3ada0469d08253a7 (diff) | |
| download | chrome-ec-22c4439064728d0d83e708724c3f3da5fd5e65b3.tar.gz | |
stm32g4: Add USB endpoint support
This CL enables USB-EP for the STM32G4 family. It also fixes backup
domain register access issues which are required for fw updates via
USB.
BUG=b:148493929
BRANCH=None
TEST=Verified on quiche that STM32G4 enumerates as an USB endpoint and
can be used successfully with fwupd.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I75e6b6e70e9ca2589ace76f0aa0facadd9e94142
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2268139
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32g4.c')
| -rw-r--r-- | chip/stm32/clock-stm32g4.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c index 941cb94327..94936b932f 100644 --- a/chip/stm32/clock-stm32g4.c +++ b/chip/stm32/clock-stm32g4.c @@ -119,6 +119,8 @@ static void stm32g4_config_low_speed_clock(void) wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); + /* Setup RTC Clock input */ + STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI); } |