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| author | Wei-Ning Huang <wnhuang@google.com> | 2017-06-19 11:42:04 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-06-21 01:02:59 -0700 |
| commit | 7eae5a320f019a2d8a0b40c060a802c0e7e03c93 (patch) | |
| tree | 48b8632984a34ed9c554a3adb4f5e0f502008c05 /chip/stm32/clock-stm32l4.c | |
| parent | 053cb4bb24a948f917b78e7e17ffdff8733d01a0 (diff) | |
| download | chrome-ec-7eae5a320f019a2d8a0b40c060a802c0e7e03c93.tar.gz | |
stm32f4: clock stm32f412 at 96MHz
On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be
clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks
can be in the right range. When APBX prescaler != 1, it results in 2x
timer clocks on both APB1 and APB2. We added a new
clock_get_timer_freq() function for stm32 to get timer specific clock
frequency so we can return 2x timer clocks when APBX != 1.
Flash latencies also need to be changed when we clock at 96MHz, the
FLASH_ACR_LATENCY defines are moved into the variant-specific switches
so each board can defined latency when setting CPU clocks.
BUG=b:38077127
TEST=`make BOARD=rose -j`, touch performance improved by 2x.
Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444
Reviewed-on: https://chromium-review.googlesource.com/539375
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32l4.c')
| -rw-r--r-- | chip/stm32/clock-stm32l4.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 18a23b8d16..c9042d10c4 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -37,6 +37,11 @@ int clock_get_freq(void) return freq; } +int clock_get_timer_freq(void) +{ + return clock_get_freq(); +} + void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) { volatile uint32_t dummy __attribute__((unused)); |