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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-05-11 14:23:31 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-15 06:42:30 +0000 |
| commit | e3dce49334a2b44e337744bc719a27c63261f35e (patch) | |
| tree | 3ee485350fafffaf53206036a3a19184068feeb5 /chip/stm32/config-stm32f03x.h | |
| parent | cba37a13d2342e4c81b0be3c84010baf3d846162 (diff) | |
| download | chrome-ec-e3dce49334a2b44e337744bc719a27c63261f35e.tar.gz | |
cleanup: Use appropriate image geometry CONFIGs
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Diffstat (limited to 'chip/stm32/config-stm32f03x.h')
| -rw-r--r-- | chip/stm32/config-stm32f03x.h | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h index 2bd4da74cb..18c8806908 100644 --- a/chip/stm32/config-stm32f03x.h +++ b/chip/stm32/config-stm32f03x.h @@ -6,7 +6,6 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00008000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ @@ -17,28 +16,6 @@ #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00001000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (16 * 1024) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE -#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect region - * contiguous. - */ -#if defined(BOARD_ZINGER) || defined(BOARD_MINIMUFFIN) -/* Not using pstate but keep some space for the public key */ -#define CONFIG_FW_PSTATE_SIZE 544 -#else -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#endif -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 |