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authorShawn Nematbakhsh <shawnn@chromium.org>2016-02-26 17:31:01 -0800
committerchrome-bot <chrome-bot@chromium.org>2016-04-19 19:19:10 -0700
commitb94c4eb99da18a276a5d4dd87f108022224c1593 (patch)
tree35d59f5c199decfe3032aa68f88eccb8e28ff1d5 /chip/stm32/config-stm32f03x.h
parentcfca3ff970d92cf73631694383927d7ff7014004 (diff)
downloadchrome-ec-b94c4eb99da18a276a5d4dd87f108022224c1593.tar.gz
snoball: Add support for proto 0.9 board
This board uses a different stm32f0 MCU and has significant architectural changes. BUG=chrome-os-partner:50549 BRANCH=None TEST=`make buildall -j`, verify snoball boots to console Change-Id: I842a3efc5e179b33bbf0441e8d4ea07fa006e3fe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329439 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32f03x.h')
-rw-r--r--chip/stm32/config-stm32f03x.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index c22855f046..246b4374cf 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -3,8 +3,15 @@
* found in the LICENSE file.
*/
-/* Memory mapping */
+#ifdef CHIP_VARIANT_STM32F03X8
+#define CONFIG_FLASH_SIZE 0x00010000
+#define CONFIG_RAM_SIZE 0x00002000
+#else
#define CONFIG_FLASH_SIZE 0x00008000
+#define CONFIG_RAM_SIZE 0x00001000
+#endif
+
+/* Memory mapping */
#define CONFIG_FLASH_BANK_SIZE 0x1000
#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
@@ -13,7 +20,6 @@
#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
#define CONFIG_RAM_BASE 0x20000000
-#define CONFIG_RAM_SIZE 0x00001000
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 32