diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2014-03-03 11:10:45 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-11 05:52:44 +0000 |
| commit | 39327cc4cd80e8f5ba30435d497c666e10cd0054 (patch) | |
| tree | 33213c418e5e72177f990ec88f1a6bc882416f10 /chip/stm32/config-stm32f07x.h | |
| parent | 0f73a129b42acfcad843203b602fbbcc8894c614 (diff) | |
| download | chrome-ec-39327cc4cd80e8f5ba30435d497c666e10cd0054.tar.gz | |
stm32: add support for STM32F0xx family
Add support for the STM32F0xx family of devices using a Cortex-M0 core
and slightly newer peripherals than F1xx family.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board.
and pass all available unit-tests on target.
Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735
Reviewed-on: https://chromium-review.googlesource.com/188983
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32f07x.h')
| -rw-r--r-- | chip/stm32/config-stm32f07x.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h new file mode 100644 index 0000000000..a40f0f1057 --- /dev/null +++ b/chip/stm32/config-stm32f07x.h @@ -0,0 +1,42 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Memory mapping */ +#define CONFIG_FLASH_BASE 0x08000000 +#define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 +#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ + +/* No page mode on STM32F, so no benefit to larger write sizes */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 + +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00002000 + +/* Size of one firmware image in flash */ +#define CONFIG_FW_IMAGE_SIZE (64 * 1024) + +#define CONFIG_FW_RO_OFF 0 +#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF +#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE + +/* + * Put pstate after RO to give RW more space and make RO write protect region + * contiguous. + */ +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT 32 + +/* Reduced history because of limited RAM */ +#undef CONFIG_CONSOLE_HISTORY +#define CONFIG_CONSOLE_HISTORY 3 |