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authorRong Chang <rongchang@chromium.org>2015-03-23 20:12:56 +0800
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-05-27 05:04:14 +0000
commit552c17543fb1e85e2143025a2dc9fdd560da5abb (patch)
tree53f41adc588d00d0adfb6d2b4ff60533a3b119b7 /chip/stm32/config-stm32f09x.h
parent937cc8a64e5971def21303e7a19a4ad9553e0ace (diff)
downloadchrome-ec-552c17543fb1e85e2143025a2dc9fdd560da5abb.tar.gz
oak: add initial support for oak board rev1
Add initial support for Oak rev1 board. This is just the EC and includes battery charging but does not include USB PD. BUG=none BRANCH=none TEST=load on oak board and get console Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Alec Berg <alecaberg@chromium.org> Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777 Reviewed-on: https://chromium-review.googlesource.com/261678
Diffstat (limited to 'chip/stm32/config-stm32f09x.h')
-rw-r--r--chip/stm32/config-stm32f09x.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
new file mode 100644
index 0000000000..fe73db195f
--- /dev/null
+++ b/chip/stm32/config-stm32f09x.h
@@ -0,0 +1,20 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_BASE 0x08000000
+#define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
+#define CONFIG_FLASH_BANK_SIZE 0x2000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
+
+/* No page mode on STM32F, so no benefit to larger write sizes */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
+
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 32