diff options
| author | Vic Yang <victoryang@chromium.org> | 2014-10-04 18:39:13 +0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-07 20:58:52 +0000 |
| commit | bd59d5bfb6a9e6fa116e19f11fe31ae98cc00e88 (patch) | |
| tree | ec9a9a4febd28a2d85c6cc193805d1b308af6b93 /chip/stm32/config-stm32f373.h | |
| parent | 08c53f231df4d7c09c396b5ccfd021fb64608cbd (diff) | |
| download | chrome-ec-bd59d5bfb6a9e6fa116e19f11fe31ae98cc00e88.tar.gz | |
Add support for STM32F373
This mostly reuses chip drivers for STM32F and STM32F0. Since this chip
doesn't fit either STM32F or STM32F0, let's use symlink to specify which
drivers to use for STM32F3.
This is just the preparatory work and it's not verified on a chip yet.
BUG=chrome-os-partner:32660
TEST=make buildall to make sure this doesn't break anything
BRANCH=None
Change-Id: I709ed49265e8f84552251a97d03b9b98496de99e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221412
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32f373.h')
| -rw-r--r-- | chip/stm32/config-stm32f373.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h new file mode 100644 index 0000000000..8ceaa51a4d --- /dev/null +++ b/chip/stm32/config-stm32f373.h @@ -0,0 +1,41 @@ +/* Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Memory mapping */ +#define CONFIG_FLASH_BASE 0x08000000 +#define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ + +/* No page mode on STM32F, so no benefit to larger write sizes */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 + +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 + +/* Size of one firmware image in flash */ +#define CONFIG_FW_IMAGE_SIZE (128 * 1024) + +#define CONFIG_FW_RO_OFF 0 +#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF +#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE + +/* + * Put pstate after RO to give RW more space and make RO write protect region + * contiguous. + */ +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT 81 + +/* STM32F3 has a larger USB RAM */ +#define CONFIG_USB_RAM_SIZE 1024 |