diff options
| author | Anton Staaf <robotboy@chromium.org> | 2014-11-10 11:23:21 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-11-11 21:46:10 +0000 |
| commit | 74a98425efd53098ed430e6817261cf6386cce3a (patch) | |
| tree | 9bcda9a90b396fb0b9e8b2d89261e993652ed7e0 /chip/stm32/config-stm32f373.h | |
| parent | 0f4a2c333ca003f47159c5988a631185ecd87eaa (diff) | |
| download | chrome-ec-74a98425efd53098ed430e6817261cf6386cce3a.tar.gz | |
USB: Fix issue with USB RAM sizes
Previously the USB RAM size was off by a factor of two
for chips that required 32-bit alignment of accesses,
even though the underlying memory was 16-bits in size.
This change adds an additional configuration for the
access size (it still assumes that the underlying memory
is 16-bits in size) and uses that to adjust the USB_RAM
memory section in the linker scripts.
This change also removes the default values for the USB
RAM from stm32/config_chip.h because they mask issues
when new chips are added. It is better for a new chip
to fail to compile until these values are provided.
Finally, this change introduces a common USB API header
so that common code doesn't need to include the STM32
specific header.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: Id118627f53e9e8ff1bd09fb51f1f9634ff495d19
Reviewed-on: https://chromium-review.googlesource.com/228833
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32f373.h')
| -rw-r--r-- | chip/stm32/config-stm32f373.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h index 2553702877..32a9d0b5fa 100644 --- a/chip/stm32/config-stm32f373.h +++ b/chip/stm32/config-stm32f373.h @@ -37,5 +37,8 @@ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 81 -/* STM32F3 has a larger USB RAM */ -#define CONFIG_USB_RAM_SIZE 512 +/* STM32F3 uses the older 4 byte aligned access mechanism */ +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t +#define CONFIG_USB_RAM_ACCESS_SIZE 4 |