diff options
| author | Scott Collyer <scollyer@google.com> | 2020-04-17 12:04:53 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-31 23:27:37 +0000 |
| commit | e2299f1afd9dfd05fc8b9ebccadf35ee3c74df8a (patch) | |
| tree | 83f9a218a68a6ccbff71576bac5464a3da726e71 /chip/stm32/config-stm32g41xb.h | |
| parent | 664002c97f1ff86f1ad4710c392051228b91d469 (diff) | |
| download | chrome-ec-e2299f1afd9dfd05fc8b9ebccadf35ee3c74df8a.tar.gz | |
stm32g4: Add flash support for stm32g4 chip family
This CL adds support for flashing stm32g4. The L4 family has the same
flash module and so that was used as basis for G4 driver. This CL
renames the l4 flash driver to capture this commonality. In addition,
the flash register definitions in G4 registers file was updated
appropriately. Previously, this section matched F4 requirements.
BUG=b:148493929
BRANCH=None
TEST=verfied usb-ep fw update completes successfully
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I6cc818c6329524924534b0566bd9d24145c86c72
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195547
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32g41xb.h')
| -rw-r--r-- | chip/stm32/config-stm32g41xb.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index 4da21c3976..1daca3c4a7 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -7,11 +7,20 @@ * Memory mapping for STM32G431xb. The STM32G431xb is a category 2 device within * the STM32G4 chip family. Category 2 devices have either 32, 64, or 128 kB of * internal flash. The 'xB' indicates 128 kB of internal flash. + * + * STM32G431x is a single bank only device consisting of 64 pages of 2 kB + * each. It supports both a mass erase or page erase feature. Note that + * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM + * for the STM32G4 chip family. The minimum erase size is 1 page. + * + * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support + * PSTATE in single bank memories with a write size > 4 bytes. */ #define CONFIG_FLASH_SIZE (128 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_SIZE +#define CONFIG_FLASH_BANK_SIZE (2 * 1024) +#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE + /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE |