diff options
| author | Scott Collyer <scollyer@google.com> | 2020-03-31 17:41:32 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-29 03:49:06 +0000 |
| commit | ad2d43937e22bea80e42af692c1593d928828ae4 (patch) | |
| tree | 6f25a60ed31fb0dbf6c73ac34178f86d9196a1ec /chip/stm32/config-stm32g41xb.h | |
| parent | dea20bc5f83286287abfd3c219391f44a2e5122a (diff) | |
| download | chrome-ec-ad2d43937e22bea80e42af692c1593d928828ae4.tar.gz | |
stm32g4: Add config-chip for stm32g41xb
This CL adds config-chip for stm32g41xb variant of the stm32g4 chip
family.
BUG=148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I418179153b631e2d7abb597fbf77374f94c4c501
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195543
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32g41xb.h')
| -rw-r--r-- | chip/stm32/config-stm32g41xb.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h new file mode 100644 index 0000000000..4da21c3976 --- /dev/null +++ b/chip/stm32/config-stm32g41xb.h @@ -0,0 +1,44 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * Memory mapping for STM32G431xb. The STM32G431xb is a category 2 device within + * the STM32G4 chip family. Category 2 devices have either 32, 64, or 128 kB of + * internal flash. The 'xB' indicates 128 kB of internal flash. + */ +#define CONFIG_FLASH_SIZE (128 * 1024) +#define CONFIG_FLASH_WRITE_SIZE 0x0004 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_SIZE + +/* Erasing 128K can take up to 2s, need to defer erase. */ +#define CONFIG_FLASH_DEFERRED_ERASE + +/* No page mode on STM32G4, so no benefit to larger write sizes */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE + +/* + * STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM + * is split into three blocks: + * • 16 Kbytes mapped at address 0x2000 0000 (SRAM1). + * • 6 Kbytes mapped at address 0x2000 4000 (SRAM2). + * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased + * at 0x2000 5800 address to be accessed by all bus controllers. + */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 + +#undef I2C_PORT_COUNT +#define I2C_PORT_COUNT 3 + +/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ +#define DMAC_COUNT 12 + +/* Use PSTATE embedded in the RO image, not in its own erase block */ +#define CONFIG_FLASH_PSTATE +#undef CONFIG_FLASH_PSTATE_BANK + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT 101 |