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| author | Randall Spangler <rspangler@chromium.org> | 2013-05-20 15:14:01 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-05-23 11:08:44 -0700 |
| commit | bd8fec9bae8fc36cc1e46bf0417f2da00530b522 (patch) | |
| tree | faec9b729b3ff9bd62c8fda2ce804bdae67fcddd /chip/stm32/config-stm32l15x.h | |
| parent | aa419b29ac9d012333a416696c7449047e085d29 (diff) | |
| download | chrome-ec-bd8fec9bae8fc36cc1e46bf0417f2da00530b522.tar.gz | |
Move flash persistent state to flash_common
Persistent state is needed by all platforms to hold the
protect-ro-at-boot flag. STM32F100 and LM4 implementations were
near-identical, and are now common code (with one #ifdef to handle the
single place where they weren't).
STM32L doesn't use pstate yet, but it'll need to. I can't simply
store the protect-ro-at-boot flag inside the WRP registers themselves
because they're still writable in EC-RW. The change to STM32L to use
pstate is coming next.
BUG=chrome-os-partner:15613
BRANCH=none
TEST=build pit, link, spring; on link and spring, do
- flashinfo -> (no flags)
- enable WP (via screw or dut-control)
- flashinfo -> wp_gpio_asserted
- flashwp enable
- flashinfo -> wp_gpio_asserted ro_at_boot
- flashwp now
- flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now)
- flashwp disable -> fails
- flashinfo -> wp_gpio_asserted ro_at_boot all_now
- reboot ap-off
- flashinfo -> wp_gpio_asserted ro_at_boot ro_now
- disable WP (via screw or dut-control)
- reboot
- flashinfo -> ro_at_boot
- flashwp disable
- flashinfo -> (no flags)
(Note that on Spring you'll need to 'forceen on' before enabling WP,
or the console will be disabled once you enable ro_at_boot and reboot.)
Change-Id: I415388b98ec8bf1d149803aaaa7fe8c7f3076c36
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56064
Diffstat (limited to 'chip/stm32/config-stm32l15x.h')
| -rw-r--r-- | chip/stm32/config-stm32l15x.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 9014ce5717..83af295f9d 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -27,7 +27,8 @@ #define CONFIG_FW_IMAGE_SIZE (64 * 1024) #define CONFIG_FW_RO_OFF 0 -#define CONFIG_FW_RO_SIZE CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ + - CONFIG_SECTION_FLASH_PSTATE_SIZE) #define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE #define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE @@ -39,12 +40,11 @@ #define CONFIG_SECTION_WP_RO_SIZE CONFIG_FW_RO_SIZE /* - * The EC uses the top bank of flash to emulate a SPI-like write protect - * register with persistent state. Put that up at the top. + * Put this after RO to give RW more space. This also makes RO write protect + * region contiguous. */ #define CONFIG_SECTION_FLASH_PSTATE_SIZE (1 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_SECTION_FLASH_PSTATE_OFF (CONFIG_FLASH_SIZE \ - - CONFIG_SECTION_FLASH_PSTATE_SIZE) +#define CONFIG_SECTION_FLASH_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 |