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| author | Louis Yung-Chieh Lo <yjlou@chromium.org> | 2012-08-17 15:46:54 +0800 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2012-08-17 01:48:30 -0700 |
| commit | 9d872b724f3e4e4d49cfb9d4040f8bab609415e5 (patch) | |
| tree | 8bef9b860fbf01fb81957b2099d9e7cf84ee33f6 /chip/stm32/config-stm32l15x.h | |
| parent | 76619f904df8ed519fac0d46d9c6c3a1956a88c2 (diff) | |
| download | chrome-ec-9d872b724f3e4e4d49cfb9d4040f8bab609415e5.tar.gz | |
Snow: WP_RO should be 0x10000 (including pstate).
To reflect the CL 00799d5 that moves the pstate to 0xf000.
BUG=chrome-os-partner:12799
TEST=Build in chroot.
snow: WP_RO is changed from 0:0xf000 --> 0:0x10000.
daisy: WP_RO is unchanged.
link: WP_RO is unchanged.
Change-Id: I572bae3f624744e60d13a762875211beffc6c516
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/30670
Reviewed-by: Vic Yang <victoryang@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32l15x.h')
| -rw-r--r-- | chip/stm32/config-stm32l15x.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 5a3fef59a8..ef913bbc0c 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -35,6 +35,8 @@ #define CONFIG_SECTION_RO_SIZE CONFIG_FW_RO_SIZE #define CONFIG_SECTION_RW_OFF CONFIG_FW_RW_OFF #define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE +#define CONFIG_SECTION_WP_RO_OFF CONFIG_FW_RO_OFF +#define CONFIG_SECTION_WP_RO_SIZE CONFIG_FW_RO_SIZE /* * The EC uses the top bank of flash to emulate a SPI-like write protect |