diff options
| author | Randall Spangler <rspangler@chromium.org> | 2012-07-17 13:51:44 -0700 |
|---|---|---|
| committer | Randall Spangler <rspangler@chromium.org> | 2012-07-18 13:48:46 -0700 |
| commit | ad2268e7396abc6ff094376eedec2402b06f3b21 (patch) | |
| tree | 4ddfbb8b0bafbefc4e709173a4c743f52086ae94 /chip/stm32/config-stm32l15x.h | |
| parent | 2bee304abda0f51bbc3d673daae26e583fb7ca55 (diff) | |
| download | chrome-ec-ad2268e7396abc6ff094376eedec2402b06f3b21.tar.gz | |
Simplify flash protection, part 1
1. If the flash protection state is locked, RO firmware is explicitly locked.
2. Protecting flash now locks the entire flash.
BUG=chrome-os-partner:11150
TEST=manual
flashinfo -> nothing protected
flashwp now
flashinfo -> unlocked,applied; everything protected
reboot
flashinfo -> nothing protected
flashwp lock ->
flashinfo -> locked,applied; now has 40 Y's at start and 1 at end
reboot
flashinfo -> locked,applied; now has 40 Y's at start and 1 at end
remove WP screw
reboot
flashinfo -> locked, not applied; nothing protected
flashwp unlock
flashinfo -> nothing protected
Change-Id: I2cf0e8bfe82ab7a5bf88b9161b7a05b889cae71a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27717
Diffstat (limited to 'chip/stm32/config-stm32l15x.h')
| -rw-r--r-- | chip/stm32/config-stm32l15x.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 15b37eb956..63d9b0d323 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -5,7 +5,8 @@ /* Memory mapping */ #define CONFIG_FLASH_BASE 0x08000000 -#define CONFIG_FLASH_SIZE 0x00020000 +#define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000 +#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 #define CONFIG_RAM_BASE 0x20000000 #define CONFIG_RAM_SIZE 0x00004000 @@ -23,12 +24,13 @@ #define CONFIG_SECTION_RW_OFF CONFIG_FW_RW_OFF #define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE -/* no keys for now */ -#define CONFIG_VBOOT_ROOTKEY_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) -#define CONFIG_VBLOCK_RW_OFF (CONFIG_FW_RW_OFF + CONFIG_FW_RW_SIZE) -#define CONFIG_VBOOT_ROOTKEY_SIZE 0 -#define CONFIG_VBLOCK_SIZE 0 - +/* + * The EC uses the top bank of flash to emulate a SPI-like write protect + * register with persistent state. Put that up at the top. + */ +#define CONFIG_SECTION_FLASH_PSTATE_SIZE (1 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_SECTION_FLASH_PSTATE_OFF (CONFIG_FLASH_SIZE \ + - CONFIG_SECTION_FLASH_PSTATE_SIZE) /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 |