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| author | Randall Spangler <rspangler@chromium.org> | 2013-05-24 15:07:27 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-06-03 14:32:38 -0700 |
| commit | b490e866dc14b55a99e53d14ade4543daeba157a (patch) | |
| tree | c005129068632cbebb8684c96810ba60f28bbd15 /chip/stm32/config-stm32l15x.h | |
| parent | e52aba6ecac45d2c27acc78316e835620840408a (diff) | |
| download | chrome-ec-b490e866dc14b55a99e53d14ade4543daeba157a.tar.gz | |
Clean up flash section defines and increase lm4 image size
The firmware defines had two almost-identical sets. Coalesce into one
consistent set.
Link had 256 KB flash, but only allowed 2 80KB images. Future
LM4-based platforms (slippy/peppy/falco/etc) will now use the entire
flash, with RO=124KB, pstate=4KB, RW=128KB. This matches what the
STM32 platforms do, where pstate is contiguous with the RO firmware.
No functional change to STM32-based platforms.
BUG=chrome-os-partner:19176
BRANCH=none
TEST=build all platforms and dump_fmap ec.bin.
- stm32-based platforms should report RO=61440@0, RW=65536@0x10000
- link should report RO=81920@0, RW=81920@0x14000
- slippy should report RO=129024@0, RW=131072@0x20000
Change-Id: I20b1d95c16250d9a5d228ead06eef03d96548823
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56655
Diffstat (limited to 'chip/stm32/config-stm32l15x.h')
| -rw-r--r-- | chip/stm32/config-stm32l15x.h | 24 |
1 files changed, 9 insertions, 15 deletions
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index dda4ebc90f..eac9347ecb 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -17,25 +17,19 @@ /* Size of one firmware image in flash */ #define CONFIG_FW_IMAGE_SIZE (64 * 1024) -#define CONFIG_FW_RO_OFF 0 -#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ - - CONFIG_SECTION_FLASH_PSTATE_SIZE) -#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE - -#define CONFIG_SECTION_RO_OFF CONFIG_FW_RO_OFF -#define CONFIG_SECTION_RO_SIZE CONFIG_FW_RO_SIZE -#define CONFIG_SECTION_RW_OFF CONFIG_FW_RW_OFF -#define CONFIG_SECTION_RW_SIZE CONFIG_FW_RW_SIZE -#define CONFIG_SECTION_WP_RO_OFF CONFIG_FW_RO_OFF -#define CONFIG_SECTION_WP_RO_SIZE CONFIG_FW_RO_SIZE +#define CONFIG_FW_RO_OFF 0 +#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE +#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF +#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE /* - * Put this after RO to give RW more space. This also makes RO write protect + * Put pstate after RO to give RW more space and make RO write protect * region contiguous. */ -#define CONFIG_SECTION_FLASH_PSTATE_SIZE (1 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_SECTION_FLASH_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 |