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| author | Vincent Palatin <vpalatin@chromium.org> | 2017-02-14 11:06:34 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-17 01:47:29 -0800 |
| commit | ad401765141ef75cdee7845082294dfa75f75697 (patch) | |
| tree | 6e2c6a5ea14361c61222065f2bacae3448c07dbd /chip/stm32/config-stm32l442.h | |
| parent | 484ef121193865225ddbc3a0b848db7f5384f836 (diff) | |
| download | chrome-ec-ad401765141ef75cdee7845082294dfa75f75697.tar.gz | |
stm32: add support for STM32L442
Should be close to the STM32L476 in the STM32L4 family.
Slightly different flash/RAM.
It's currently running from the internal clock (HSI) at 16Mhz,
we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us
the PLL locking time).
The internal flash write/erase/protection is still not implemented for
the whole STM32L4 family.
Upgrade the SPI master support and verify that the TX works.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=make BOARD=eve_fp
run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES)
Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e
Reviewed-on: https://chromium-review.googlesource.com/442466
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/stm32/config-stm32l442.h')
| -rw-r--r-- | chip/stm32/config-stm32l442.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h new file mode 100644 index 0000000000..e9f3e04c53 --- /dev/null +++ b/chip/stm32/config-stm32l442.h @@ -0,0 +1,24 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Memory mapping */ +#define CONFIG_FLASH_SIZE 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ + +/* Ideal write size in page-mode */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ + +/* + * SRAM1 (48kB) at 0x20000000 + * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) + * so they are contiguous. + */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT 82 |