diff options
| author | Rong Chang <rongchang@google.com> | 2017-02-22 11:32:39 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-27 16:56:24 -0800 |
| commit | ec98dbfb35bb22bb6b9096eceedda93c9f88f85c (patch) | |
| tree | 17a36638e971abafe0ad4b7a452a2078f47a67e4 /chip/stm32/config_chip.h | |
| parent | 31cfc63b80ea8f5b778e6c3f568f325a6064244a (diff) | |
| download | chrome-ec-ec98dbfb35bb22bb6b9096eceedda93c9f88f85c.tar.gz | |
stm32f09x: fix flash protection offset
STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB),
which doesn't fit the layout requirement in config_std_internal_flash.h.
This CL hardcodes the layout and flash bank mapping.
BUG=chrome-os-partner:62372
BUG=chromium:694972
TEST=load on elm and manually enable write protect using flashrom
# flashrom -p ec:dev=0 --wp-enable
check ec console write protect option bytes, bank 31 is writable
> rw 0x1ffff808
read 0x1ffff808 = 0xff00ff00
> rw 0x1ffff80c
read 0x1ffff80c = 0x7f80ff00
BRANCH=oak
Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446176
Diffstat (limited to 'chip/stm32/config_chip.h')
| -rw-r--r-- | chip/stm32/config_chip.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 0b79153113..2253639f83 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -67,7 +67,7 @@ /* Program is run directly from storage */ #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE -#if !defined(CHIP_VARIANT_STM32F446) +#if !defined(CHIP_VARIANT_STM32F446) && !defined(CHIP_VARIANT_STM32F09X) /* Compute the rest of the flash params from these */ #include "config_std_internal_flash.h" #endif |