diff options
| author | Vic Yang <victoryang@google.com> | 2015-02-04 11:28:53 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-02-10 10:47:07 +0000 |
| commit | 049463f8ad985f9cb996caa7dbc5438383bd3084 (patch) | |
| tree | 93ff78695657a998919c6d6e28101cd158489368 /chip/stm32/crc_hw.h | |
| parent | a9ae00b10129feca28713a7b88978ff6cfe7c2a6 (diff) | |
| download | chrome-ec-049463f8ad985f9cb996caa7dbc5438383bd3084.tar.gz | |
stm32: Add delay after enabling peripheral clock
We need a dummy read after enabling AHB peripheral clock before we can
access the peripheral. For APB, we also need a dummy read for STM32F3.
BRANCH=All affected
BUG=chrome-os-partner:33007
TEST=make buildall
Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/246181
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
Diffstat (limited to 'chip/stm32/crc_hw.h')
| -rw-r--r-- | chip/stm32/crc_hw.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h index c1a97da842..edaf3b5d32 100644 --- a/chip/stm32/crc_hw.h +++ b/chip/stm32/crc_hw.h @@ -7,12 +7,15 @@ #define _CRC_HW_H /* CRC-32 hardware implementation with USB constants */ +#include "clock.h" #include "registers.h" static inline void crc32_init(void) { /* switch on CRC controller */ STM32_RCC_AHBENR |= 1 << 6; /* switch on CRC controller */ + /* Delay 1 AHB clock cycle after the clock is enabled */ + clock_wait_bus_cycles(BUS_AHB, 1); /* reset CRC state */ STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT | STM32_CRC_CR_REV_IN_WORD; |