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author | Bossen WU <bossen.wu@stmicro.corp-partner.google.com> | 2021-06-21 17:36:21 +0800 |
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committer | Commit Bot <commit-bot@chromium.org> | 2021-07-01 04:11:20 +0000 |
commit | 31bd47333d5fbfb1d237cb5e86fe532a348a0a31 (patch) | |
tree | 6cfd306b78c216163e0d37217565b979116f1f51 /chip/stm32/dma.c | |
parent | d1890dfc09eb9ef79fdea2c0dab0c642d6c9436a (diff) | |
download | chrome-ec-31bd47333d5fbfb1d237cb5e86fe532a348a0a31.tar.gz |
stm32: add stm32l431 ec in chip/stm32 : dma
stm32l431 related driver: dma
The stm32l476g-eval is the only board which would be impacted.
BRANCH=main
BUG=b:188117811
TEST=make buildall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: Ia513875963c2c65f6b63605fc113f139656a4028
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975520
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'chip/stm32/dma.c')
-rw-r--r-- | chip/stm32/dma.c | 35 |
1 files changed, 29 insertions, 6 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index cd6038b2aa..e29b8f487b 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -39,6 +39,17 @@ static int dma_get_irq(enum dma_channel channel) return channel > STM32_DMAC_CH3 ? STM32_IRQ_DMA_CHANNEL_4_7 : STM32_IRQ_DMA_CHANNEL_2_3; +#elif defined(CHIP_FAMILY_STM32L4) + if (channel < STM32_DMAC_PER_CTLR) + return STM32_IRQ_DMA_CHANNEL_1 + channel; + else { + if (channel <= STM32_DMAC_CH13) + return STM32_IRQ_DMA2_CHANNEL1 + + (channel - STM32_DMAC_PER_CTLR); + else + return STM32_IRQ_DMA2_CHANNEL6 + + (channel - STM32_DMAC_PER_CTLR - 5); + } #else if (channel < STM32_DMAC_PER_CTLR) return STM32_IRQ_DMA_CHANNEL_1 + channel; @@ -99,6 +110,7 @@ void dma_disable_all(void) for (ch = 0; ch < STM32_DMAC_COUNT; ch++) { stm32_dma_chan_t *chan = dma_get_channel(ch); + chan->ccr &= ~STM32_DMA_CCR_EN; } } @@ -114,8 +126,8 @@ void dma_disable_all(void) * STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx * 0 for rx */ -static void prepare_channel(enum dma_channel channel, unsigned count, - void *periph, void *memory, unsigned flags) +static void prepare_channel(enum dma_channel channel, unsigned int count, + void *periph, void *memory, unsigned int flags) { stm32_dma_chan_t *chan = dma_get_channel(channel); uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; @@ -141,7 +153,7 @@ void dma_go(stm32_dma_chan_t *chan) chan->ccr |= STM32_DMA_CCR_EN; } -void dma_prepare_tx(const struct dma_option *option, unsigned count, +void dma_prepare_tx(const struct dma_option *option, unsigned int count, const void *memory) { /* @@ -153,10 +165,11 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count, option->flags); } -void dma_start_rx(const struct dma_option *option, unsigned count, +void dma_start_rx(const struct dma_option *option, unsigned int count, void *memory) { stm32_dma_chan_t *chan = dma_get_channel(option->channel); + prepare_channel(option->channel, count, option->periph, memory, STM32_DMA_CCR_MINC | option->flags); dma_go(chan); @@ -211,7 +224,7 @@ void dma_test(enum dma_channel channel) stm32_dma_chan_t *chan = dma_get_channel(channel); uint32_t ctrl; char periph[16], memory[16]; - unsigned count = sizeof(periph); + unsigned int count = sizeof(periph); int i; memset(memory, '\0', sizeof(memory)); @@ -275,6 +288,7 @@ int dma_wait(enum dma_channel channel) static inline void _dma_wake_callback(void *cb_data) { task_id_t id = (task_id_t)(int)cb_data; + if (id != TASK_ID_INVALID) task_set_event(id, TASK_EVENT_DMA_TC); } @@ -369,7 +383,7 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1); (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ } \ DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ - CONCAT2(dma_event_interrupt_channel_, x), 1); + CONCAT2(dma_event_interrupt_channel_, x), 1) DECLARE_DMA_IRQ(1); DECLARE_DMA_IRQ(2); @@ -382,6 +396,15 @@ DECLARE_DMA_IRQ(7); DECLARE_DMA_IRQ(9); DECLARE_DMA_IRQ(10); #endif +#ifdef CHIP_FAMILY_STM32L4 +DECLARE_DMA_IRQ(9); +DECLARE_DMA_IRQ(10); +DECLARE_DMA_IRQ(11); +DECLARE_DMA_IRQ(12); +DECLARE_DMA_IRQ(13); +DECLARE_DMA_IRQ(14); +DECLARE_DMA_IRQ(15); +#endif #endif /* CHIP_FAMILY_STM32F0 */ #endif /* CONFIG_DMA_DEFAULT_HANDLERS */ |