diff options
| author | Alec Berg <alecaberg@chromium.org> | 2014-07-01 11:31:41 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-07-03 05:25:13 +0000 |
| commit | 9ba7bd4284eb8aac2347f3a71fc830c59ccbe387 (patch) | |
| tree | 3ffb0cbe850452916999032bd0aa58fe23886414 /chip/stm32/dma.c | |
| parent | 64733430754848bfb1f67c87c4c9142564270583 (diff) | |
| download | chrome-ec-9ba7bd4284eb8aac2347f3a71fc830c59ccbe387.tar.gz | |
pd: clean up beg/end transitions of PD comms
Fix the beginning and end of BMC PD communication:
- Initial transmission within 1us of taking control of CC line
- CC line released between 1us and 23us after last edge
- If final bit is a 0, then add two 1 bits to the end
- No garbage after the final bit
BUG=chrome-os-partner:30132
BRANCH=none
TEST=tested with a fruitpie, samus, and zinger.
verified timing on scope.
Change-Id: Ie45695eb367a7554cf5d5b76b6fbdf1e3fc85d29
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/206453
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/dma.c')
| -rw-r--r-- | chip/stm32/dma.c | 53 |
1 files changed, 51 insertions, 2 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index e648b7418e..75073b4db6 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -27,7 +27,16 @@ static task_id_t id[STM32_DMAC_COUNT]; */ static int dma_get_irq(enum dma_channel channel) { +#ifdef CHIP_FAMILY_STM32F0 + if (channel == STM32_DMAC_CH1) + return STM32_IRQ_DMA_CHANNEL_1; + + return channel > STM32_DMAC_CH3 ? + STM32_IRQ_DMA_CHANNEL_4_7 : + STM32_IRQ_DMA_CHANNEL_2_3; +#else return STM32_IRQ_DMA_CHANNEL_1 + channel; +#endif } /* @@ -241,7 +250,47 @@ void dma_clear_isr(enum dma_channel channel) dma->ifcr |= STM32_DMA_ISR_ALL(channel); } -#ifndef CHIP_FAMILY_STM32F0 +#ifdef CHIP_FAMILY_STM32F0 +void dma_event_interrupt_channel_1(void) +{ + if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) { + dma_clear_isr(STM32_DMAC_CH1); + if (id[STM32_DMAC_CH1] != TASK_ID_INVALID) + task_wake(id[STM32_DMAC_CH1]); + } +} +DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 3); + +void dma_event_interrupt_channel_2_3(void) +{ + int i; + + for (i = STM32_DMAC_CH2; i <= STM32_DMAC_CH3; i++) { + if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { + dma_clear_isr(i); + if (id[i] != TASK_ID_INVALID) + task_wake(id[i]); + } + } +} +DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 3); + +void dma_event_interrupt_channel_4_7(void) +{ + int i; + + for (i = STM32_DMAC_CH4; i <= STM32_DMAC_CH7; i++) { + if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { + dma_clear_isr(i); + if (id[i] != TASK_ID_INVALID) + task_wake(id[i]); + } + } +} +DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 3); + +#else /* !CHIP_FAMILY_STM32F0 */ + void dma_event_interrupt_channel_4(void) { dma_clear_isr(STM32_DMAC_CH4); @@ -273,4 +322,4 @@ void dma_event_interrupt_channel_7(void) task_wake(id[STM32_DMAC_CH7]); } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_7, dma_event_interrupt_channel_7, 3); -#endif /* !CHIP_FAMILY_STM32F0 */ +#endif /* CHIP_FAMILY_STM32F0 */ |