diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2014-03-06 16:02:58 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-11 05:52:37 +0000 |
| commit | 7aab81edce830e15134b52256ad3186e08951b10 (patch) | |
| tree | e6197b4cc038172426b046153fc512ddefb019e8 /chip/stm32/dma.c | |
| parent | 0e3ff013cc7814705137d373218ea7bfa0f94c2c (diff) | |
| download | chrome-ec-7aab81edce830e15134b52256ad3186e08951b10.tar.gz | |
force the compiler to use a valid register allocation for irq handlers
When we are calling the re-scheduling routine at the end of an irq
handling routine, we need to ensure that the high registers are not
currently saved on the system stack.
On Cortex-M3/M4, the compiler is normally doing tail-call optimization
there and behaving properly, but this fixes the fact that insanely large
interrupt handling routines where sometimes not compile and not running
properly (aka issue 24515).
This also prepares for one more core-specific DECLARE_IRQ routine on
Cortex-M0.
Note: now on, the IRQ handling routines should no longer be "static".
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:24515
TEST=make -j buildall
revert the workaround for 24515, see the issue happening only without
this CL.
Change-Id: Ic419369231925568df05815fd079ed191a5446db
Reviewed-on: https://chromium-review.googlesource.com/189153
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/dma.c')
| -rw-r--r-- | chip/stm32/dma.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index 06da15e1b6..f6dfd89aa8 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -238,7 +238,7 @@ void dma_clear_isr(enum dma_channel channel) dma->ifcr |= STM32_DMA_ISR_ALL(channel); } -static void dma_event_interrupt_channel_4(void) +void dma_event_interrupt_channel_4(void) { dma_clear_isr(STM32_DMAC_CH4); if (id[STM32_DMAC_CH4] != TASK_ID_INVALID) @@ -246,7 +246,7 @@ static void dma_event_interrupt_channel_4(void) } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4, dma_event_interrupt_channel_4, 3); -static void dma_event_interrupt_channel_5(void) +void dma_event_interrupt_channel_5(void) { dma_clear_isr(STM32_DMAC_CH5); if (id[STM32_DMAC_CH5] != TASK_ID_INVALID) @@ -254,7 +254,7 @@ static void dma_event_interrupt_channel_5(void) } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_5, dma_event_interrupt_channel_5, 3); -static void dma_event_interrupt_channel_6(void) +void dma_event_interrupt_channel_6(void) { dma_clear_isr(STM32_DMAC_CH6); if (id[STM32_DMAC_CH6] != TASK_ID_INVALID) @@ -262,7 +262,7 @@ static void dma_event_interrupt_channel_6(void) } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_6, dma_event_interrupt_channel_6, 3); -static void dma_event_interrupt_channel_7(void) +void dma_event_interrupt_channel_7(void) { dma_clear_isr(STM32_DMAC_CH7); if (id[STM32_DMAC_CH7] != TASK_ID_INVALID) |