diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2012-10-11 16:12:28 -0700 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2012-10-11 23:32:26 -0700 |
| commit | 94063c0f35d18cdfab0b678ee965220284a80f4d (patch) | |
| tree | 5ad002be1edece2421642c8f80238a02e4fb89d2 /chip/stm32/dma.c | |
| parent | 1edad9de1196496f1844b8819b1ab8f9789712d7 (diff) | |
| download | chrome-ec-94063c0f35d18cdfab0b678ee965220284a80f4d.tar.gz | |
stm32: support DMA on I2C1
Each I2C controller needs to use a fixed pair of DMA channels.
The former code was hardcoded for I2C2. We now use the board
configuration to decide between I2C1 and I2C2 DMA channels.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:15185
TEST=make BOARD=snow && make BOARD=spring && make BOARD=daisy
run on Spring and Snow and see we can communicate both with the PMU
(using "pmu" EC console command) and the AP (answering U-Boot host command)
Change-Id: Ifd6806205b443c623e3db09fb1a2d5804bb94214
Reviewed-on: https://gerrit.chromium.org/gerrit/35355
Reviewed-by: Charlie Mooney <charliemooney@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/dma.c')
| -rw-r--r-- | chip/stm32/dma.c | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index ab8e8f2d58..c5d1c5e493 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -278,16 +278,32 @@ struct dma_ctlr *dma_get_ctlr(int channel) static void dma_event_interrupt_channel_4(void) { - dma_clear_isr(DMAC_I2C_TX); - if (id[DMAC_I2C_TX] != TASK_ID_INVALID) - task_wake(id[DMAC_I2C_TX]); + dma_clear_isr(DMAC_I2C2_TX); + if (id[DMAC_I2C2_TX] != TASK_ID_INVALID) + task_wake(id[DMAC_I2C2_TX]); } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4, dma_event_interrupt_channel_4, 3); static void dma_event_interrupt_channel_5(void) { - dma_clear_isr(DMAC_I2C_RX); - if (id[DMAC_I2C_RX] != TASK_ID_INVALID) - task_wake(id[DMAC_I2C_RX]); + dma_clear_isr(DMAC_I2C2_RX); + if (id[DMAC_I2C2_RX] != TASK_ID_INVALID) + task_wake(id[DMAC_I2C2_RX]); } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_5, dma_event_interrupt_channel_5, 3); + +static void dma_event_interrupt_channel_6(void) +{ + dma_clear_isr(DMAC_I2C1_TX); + if (id[DMAC_I2C1_TX] != TASK_ID_INVALID) + task_wake(id[DMAC_I2C1_TX]); +} +DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_6, dma_event_interrupt_channel_6, 3); + +static void dma_event_interrupt_channel_7(void) +{ + dma_clear_isr(DMAC_I2C1_RX); + if (id[DMAC_I2C1_RX] != TASK_ID_INVALID) + task_wake(id[DMAC_I2C1_RX]); +} +DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_7, dma_event_interrupt_channel_7, 3); |