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authorVic Yang <victoryang@chromium.org>2014-10-14 10:05:43 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-10-15 23:56:27 +0000
commitf8fd63f135b5922900ceeb345857070e814f8877 (patch)
treed93f66806f14465810b263e30d49a3e610430acf /chip/stm32/flash-stm32f0.c
parent847eb1ec44aa43c761799b522b0449bdfc31269a (diff)
downloadchrome-ec-f8fd63f135b5922900ceeb345857070e814f8877.tar.gz
Fix incorrect valid and writable flash flags
The valid and writable flags the EC sends back to the AP are incorrect. They are a little bit different on differnt chips, so let's move it to flash physical layer. This is not any causing problem, but we should fix this. BUG=chrome-os-partner:32745 TEST=make buildall BRANCH=samus Change-Id: Ibcda5ae770f5ea02cde094490997a5bc447df88f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222661 Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/flash-stm32f0.c')
-rw-r--r--chip/stm32/flash-stm32f0.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c
index bbf3574c21..85e65c6ac4 100644
--- a/chip/stm32/flash-stm32f0.c
+++ b/chip/stm32/flash-stm32f0.c
@@ -42,3 +42,30 @@ int flash_physical_restore_state(void)
/* Nothing to restore */
return 0;
}
+
+uint32_t flash_physical_get_valid_flags(void)
+{
+ return EC_FLASH_PROTECT_RO_AT_BOOT |
+ EC_FLASH_PROTECT_ALL_AT_BOOT |
+ EC_FLASH_PROTECT_RO_NOW |
+ EC_FLASH_PROTECT_ALL_NOW;
+}
+
+uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
+{
+ uint32_t ret = 0;
+
+ /* If RO protection isn't enabled, its at-boot state can be changed. */
+ if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
+ ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
+
+ /*
+ * RW at-boot state can be set if WP GPIO is asserted and can always
+ * be cleared.
+ */
+ if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
+ EC_FLASH_PROTECT_GPIO_ASSERTED))
+ ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
+
+ return ret;
+}