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| author | Vincent Palatin <vpalatin@chromium.org> | 2017-08-13 13:16:38 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-08-18 16:46:34 -0700 |
| commit | 3cbdff8b1bc3f8621a1c6801340c45b0951aee17 (patch) | |
| tree | c9585128735c06d6d6cf94ebe066ca21f2f021c8 /chip/stm32/flash-stm32f3.c | |
| parent | b6d83d456f0293f329c34c5005c578d87a7cf7cc (diff) | |
| download | chrome-ec-3cbdff8b1bc3f8621a1c6801340c45b0951aee17.tar.gz | |
stm32: add embryonic support for STM32F76x
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/stm32/flash-stm32f3.c')
| -rw-r--r-- | chip/stm32/flash-stm32f3.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index 6fe7df91c5..843bbf48e4 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -12,9 +12,36 @@ #include "system.h" #include "panic.h" -#ifdef CHIP_FAMILY_STM32F4 /*****************************************************************************/ /* Physical layer APIs */ +#ifdef CHIP_VARIANT_STM32F76X +/* + * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB + */ +struct ec_flash_bank const flash_bank_array[] = { + { + .count = 4, + .size_exp = __fls(SIZE_32KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_32KB), + .protect_size_exp = __fls(SIZE_32KB), + }, + { + .count = 1, + .size_exp = __fls(SIZE_128KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_128KB), + .protect_size_exp = __fls(SIZE_128KB), + }, + { + .count = (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB, + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .size_exp = __fls(SIZE_256KB), + .erase_size_exp = __fls(SIZE_256KB), + .protect_size_exp = __fls(SIZE_256KB), + }, +}; +#elif defined(CHIP_FAMILY_STM32F4) /* * 8 "erase" sectors : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB */ |