diff options
author | Nicolas Boichat <drinkcat@chromium.org> | 2018-07-06 14:30:17 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-06 22:53:15 -0700 |
commit | 71fa0298a855fc81920fe54f5e7e63f4e94913dc (patch) | |
tree | db670a34d0c91abc959dad97c3eddf82db49e475 /chip/stm32/flash-stm32h7.c | |
parent | 7d095691d8e5b445979518e0bccdc0438e397aab (diff) | |
download | chrome-ec-71fa0298a855fc81920fe54f5e7e63f4e94913dc.tar.gz |
flash-stm32h7: Fix flash_physical_erase/write at bank boundary
For example, if we just want to erase the last block of flash, this
would fail:
flasherase 0x1e0000 0x20000
As the test would think that the end of the erase operation is in a
different bank:
((offset + size) / HWBANK_SIZE != bank)
BRANCH=none
BUG=b:111190988
TEST=flasherase 0x1e0000 0x20000 works.
TEST=flasherase 0xe0000 0x20000 works.
TEST=flasherase 0xe0000 0x40000 fails (as expected)
Change-Id: I2698efcc3d03d55b32f4e1e305c5be7485358ceb
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1127802
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/flash-stm32h7.c')
-rw-r--r-- | chip/stm32/flash-stm32h7.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index ba205a46ed..318d49f133 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -187,7 +187,7 @@ int flash_physical_write(int offset, int size, const char *data) return EC_ERROR_ACCESS_DENIED; /* work on a single hardware bank at a time */ - if ((offset + size) / HWBANK_SIZE != bank) + if ((offset + size - 1) / HWBANK_SIZE != bank) return EC_ERROR_INVAL; if (unlock(bank) != EC_SUCCESS) @@ -257,7 +257,7 @@ int flash_physical_erase(int offset, int size) return EC_ERROR_ACCESS_DENIED; /* work on a single hardware bank at a time */ - if ((offset + size) / HWBANK_SIZE != bank) + if ((offset + size - 1) / HWBANK_SIZE != bank) return EC_ERROR_INVAL; if (unlock(bank) != EC_SUCCESS) |