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| author | Nicolas Boichat <drinkcat@google.com> | 2017-01-11 14:17:33 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-12 21:05:11 -0800 |
| commit | 8c12f0a53f93e12530081fcbe164dab48257e58d (patch) | |
| tree | ce2873f66b05e28ad2d9b0170c52f5856f74eb1e /chip/stm32/flash-stm32l.c | |
| parent | 14533749af1c89f3b0224092c580ebe147611299 (diff) | |
| download | chrome-ec-8c12f0a53f93e12530081fcbe164dab48257e58d.tar.gz | |
flash: Pass more precise parameter to flash_[physical_]protect_at_boot
In preparation for adding the rollback protection block, pass
EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot,
instead of an enumeration no protection/RO/ALL.
This will later allow us to protect/unprotect the rollback region only,
by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection
can be checked with flasherase/flashwrite.
TEST=On hammer (stm32f072):
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp rw; reboot => RO+RW protected
flashwp norw; reboot => only RO protected
TEST=On reef (npcx):
deassert WP, flashwp false; flashinfo => RO+RW not protected
flashwp true => only RO protected
reboot => only RO protected
flashwp rw => RO+RW protected
reboot => only RO protected
Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f
Reviewed-on: https://chromium-review.googlesource.com/430518
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/flash-stm32l.c')
| -rw-r--r-- | chip/stm32/flash-stm32l.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index ce292bb58d..f796f4efaa 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -317,20 +317,20 @@ int flash_physical_get_protect(int block) return STM32_FLASH_WRPR & (1 << block); } -int flash_physical_protect_at_boot(enum flash_wp_range range) +int flash_physical_protect_at_boot(uint32_t new_flags) { uint32_t prot; uint32_t mask = ((1 << WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; int rv; - if (range == FLASH_WP_ALL) + if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) return EC_ERROR_UNIMPLEMENTED; /* Read the current protection status */ prot = read_optb_wrp(); /* Set/clear bits */ - if (range == FLASH_WP_RO) + if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) prot |= mask; else prot &= ~mask; @@ -448,7 +448,7 @@ int flash_pre_init(void) * update to the write protect register and reboot so * it takes effect. */ - flash_protect_at_boot(FLASH_WP_RO); + flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } @@ -457,9 +457,8 @@ int flash_pre_init(void) * Write protect register was in an inconsistent state. * Set it back to a good state and reboot. */ - flash_protect_at_boot( - (prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? - FLASH_WP_RO : FLASH_WP_NONE); + flash_protect_at_boot(prot_flags & + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW | |