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| author | Jes B. Klinke <jbk@chromium.org> | 2021-08-10 10:03:18 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-25 17:27:51 +0000 |
| commit | 7dddeb52f1f4e0d44b99424a7b8c69b38f48b996 (patch) | |
| tree | e327b63228551177aaa3035e5a78297427211a48 /chip/stm32/gpio-stm32l5.c | |
| parent | 6fc57405b6f9d38edf62824cd2d2fdae1f6e5bbf (diff) | |
| download | chrome-ec-7dddeb52f1f4e0d44b99424a7b8c69b38f48b996.tar.gz | |
chip/stm32: Add initial support for STM32L5xx series
Introduce L5xx mostly as copy of L4xx, though registers-stm32l5.c is
extensively modified.
BUG=b:192262089
TEST=Compile and upload board/hyperdebug to Nucleo board
BRANCH=none
Signed-off-by: Jes B. Klinke <jbk@opentitan.org>
Change-Id: Iccc7b05e4f2dfa732559b8099cf856882401e31c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086362
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Diffstat (limited to 'chip/stm32/gpio-stm32l5.c')
| -rw-r--r-- | chip/stm32/gpio-stm32l5.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c new file mode 100644 index 0000000000..43a7db05da --- /dev/null +++ b/chip/stm32/gpio-stm32l5.c @@ -0,0 +1,68 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "clock.h" +#include "common.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "task.h" +#include "util.h" + +void gpio_enable_clocks(void) +{ + /* + * Enable all GPIOs clocks + * + * TODO(crosbug.com/p/23770): only enable the banks we need to, + * and support disabling some of them in low-power idle. + */ + STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK; + + /* Delay 1 AHB clock cycle after the clock is enabled */ + clock_wait_bus_cycles(BUS_AHB, 1); +} + +static void gpio_init(void) +{ + /* Enable IRQs now that pins are set up */ + task_enable_irq(STM32_IRQ_EXTI0); + task_enable_irq(STM32_IRQ_EXTI1); + task_enable_irq(STM32_IRQ_EXTI2); + task_enable_irq(STM32_IRQ_EXTI3); + task_enable_irq(STM32_IRQ_EXTI4); + task_enable_irq(STM32_IRQ_EXTI5); + task_enable_irq(STM32_IRQ_EXTI6); + task_enable_irq(STM32_IRQ_EXTI7); + task_enable_irq(STM32_IRQ_EXTI8); + task_enable_irq(STM32_IRQ_EXTI9); + task_enable_irq(STM32_IRQ_EXTI10); + task_enable_irq(STM32_IRQ_EXTI11); + task_enable_irq(STM32_IRQ_EXTI12); + task_enable_irq(STM32_IRQ_EXTI13); + task_enable_irq(STM32_IRQ_EXTI14); + task_enable_irq(STM32_IRQ_EXTI15); + +} +DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); + +DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI5, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI6, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI7, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI8, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI9, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI10, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI11, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI12, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI13, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI14, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI15, gpio_interrupt, 1); + +#include "gpio-f0-l.c" |