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authorNicolas Boichat <drinkcat@chromium.org>2018-08-29 15:45:59 +0800
committerchrome-bot <chrome-bot@chromium.org>2018-10-30 08:42:56 -0700
commit5e6f10ed2f78b644371abb38e2e1f9a5124bc288 (patch)
treee9a9cccb4059835d181a983d62e3b778851d3c02 /chip/stm32/gpio.c
parentf420a49e257769b94a991416d0ebf4a30f5c9668 (diff)
downloadchrome-ec-5e6f10ed2f78b644371abb38e2e1f9a5124bc288.tar.gz
kukui/emmc: Share EXTI15 interrupt between SPI and eMMC
We never need to have interrupts enabled on both SPI1_NSS and EMMC_CMD, so we can actually share the interrupt selection EXTI15 between the 2 pins. This frees up PA14 (and EXTI14) for future interrupt needs. To make sure that we can answer host commands as soon as the AP as booted, we quickly poll for the eMMC bootblock switch to turn away from EC, and switch interrupt from eMMC to SPI. Also, we clear exit_events in chip/stm32/gpio.c, so that we do not report a override warning if we disable then re-enable another interrupt on the same EXTI. BRANCH=none BUG=b:113370127 TEST=Boot kukui rev1, check that EC commands works after boot Change-Id: Ib1f0a56a9f37e1bda01dc4e6b55734196bb3ff50 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1195345 Reviewed-by: Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'chip/stm32/gpio.c')
-rw-r--r--chip/stm32/gpio.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c
index 7108d4a10e..a8415cce1b 100644
--- a/chip/stm32/gpio.c
+++ b/chip/stm32/gpio.c
@@ -105,6 +105,7 @@ int gpio_enable_interrupt(enum gpio_signal signal)
int gpio_disable_interrupt(enum gpio_signal signal)
{
const struct gpio_info *g = gpio_list + signal;
+ uint32_t bit;
/* Fail if not implemented or no interrupt handler */
if (!g->mask || signal >= GPIO_IH_COUNT)
@@ -112,6 +113,10 @@ int gpio_disable_interrupt(enum gpio_signal signal)
STM32_EXTI_IMR &= ~g->mask;
+ bit = GPIO_MASK_TO_NUM(g->mask);
+
+ exti_events[bit] = 0;
+
return EC_SUCCESS;
}