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authorRandall Spangler <rspangler@chromium.org>2013-06-24 14:22:03 -0700
committerChromeBot <chrome-bot@google.com>2013-06-26 09:08:23 -0700
commit8e72f58ac4dd7a19069a58cde3ab1e91e8874091 (patch)
treeeb459655af25b905199e031f3dfeed92349199ff /chip/stm32/hwtimer.c
parent67c275f849939dfa9993175f1704cb80b11a40b3 (diff)
downloadchrome-ec-8e72f58ac4dd7a19069a58cde3ab1e91e8874091.tar.gz
pit: Clean up timer init code
Power LED PWM now uses the same functions as the hardware timer. BUG=chrome-os-partner:20414 BRANCH=none TEST=Suspend system. Power button LED pulses smoothly still. Change-Id: Ib5ca6655d815462baaf68600ad14c4c0c680a6af Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59838
Diffstat (limited to 'chip/stm32/hwtimer.c')
-rw-r--r--chip/stm32/hwtimer.c41
1 files changed, 31 insertions, 10 deletions
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
index 059814de8a..8067843734 100644
--- a/chip/stm32/hwtimer.c
+++ b/chip/stm32/hwtimer.c
@@ -160,14 +160,35 @@ static void __hw_clock_source_irq(void)
DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1);
DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1);
-void __hw_timer_enable_clock(int n)
+void __hw_timer_enable_clock(int n, int enable)
{
- if (n == 1) /* STM32F only */
- STM32_RCC_APB2ENR |= 1 << 11;
- else if (n >= 2 && n <= 7)
- STM32_RCC_APB1ENR |= 1 << (n - 2);
- else if (n >= 9 && n <= 11) /* STM32L only */
- STM32_RCC_APB2ENR |= 1 << (n - 7);
+ volatile uint32_t *reg;
+ uint32_t mask = 0;
+
+#if defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
+ if (n == 1) {
+ reg = &STM32_RCC_APB2ENR;
+ mask = 1 << 11;
+ }
+#elif defined(CHIP_VARIANT_stm32l15x)
+ if (n >= 9 && n <= 11) {
+ reg = &STM32_RCC_APB2ENR;
+ mask = 1 << (n - 7);
+ }
+#endif
+
+ if (n >= 2 && n <= 7) {
+ reg = &STM32_RCC_APB1ENR;
+ mask = 1 << (n - 2);
+ }
+
+ if (!mask)
+ return;
+
+ if (enable)
+ *reg |= mask;
+ else
+ *reg &= ~mask;
}
static void update_prescaler(void)
@@ -194,8 +215,8 @@ int __hw_clock_source_init(uint32_t start_t)
*/
/* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */
- __hw_timer_enable_clock(TIM_CLOCK_MSB);
- __hw_timer_enable_clock(TIM_CLOCK_LSB);
+ __hw_timer_enable_clock(TIM_CLOCK_MSB, 1);
+ __hw_timer_enable_clock(TIM_CLOCK_LSB, 1);
/*
* Timer configuration : Upcounter, counter disabled, update event only
@@ -280,7 +301,7 @@ void hwtimer_setup_watchdog(void)
struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
/* Enable clock */
- __hw_timer_enable_clock(TIM_WATCHDOG);
+ __hw_timer_enable_clock(TIM_WATCHDOG, 1);
/*
* Timer configuration : Down counter, counter disabled, update