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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-02-28 13:50:39 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-05 00:21:20 -0800 |
| commit | 55855fd593912aa82cb59c9fa0eafe9c6990d91d (patch) | |
| tree | 678912e5f9dd373ef54df873aa541ba5672bee5f /chip/stm32/hwtimer32.c | |
| parent | d87c684288ed1c40615b1c2784ba426ad9655dcd (diff) | |
| download | chrome-ec-55855fd593912aa82cb59c9fa0eafe9c6990d91d.tar.gz | |
stm32: crank up CPU PLL frequency to 400Mhz on STM32H743
Set the PLL frequency to 400 Mhz (max value) and the AHB frequency to
200 Mhz.
Fix the PLL clocking code for STM32H7 :
- fix the frequency computation.
- adjust the timer divider depending on the system clock.
- the 64Mhz HSI is already setup properly at startup, takes it into
account.
- set the SPI ports on the fixed 64-Mhz HSI, so clocking changes don't
mess up their frequencies or stability.
Note: this is just modifying the CPU frequency when the system is
clocked by the PLL, by default the system is still clocked by the 64-Mhz
HSI. Currently, one have to use the 'clock pll' console command to test
this PLL mode, some code will be added soon to switch on-demand for
heavy computations.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508, b:72879097
TEST=On ZerbleBarn, do 'clock pll', check 'gettime' against wall clock,
run image capture and enrollment.
TEST=on ZerbleBarn, verify on the scope that the SPI master frequency is
4 Mhz in both configuration.
Change-Id: I92a2216999337cf9831fb5dfc2797ab1cce71a8f
Reviewed-on: https://chromium-review.googlesource.com/941226
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/hwtimer32.c')
| -rw-r--r-- | chip/stm32/hwtimer32.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index c04f326770..683d5ff669 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -130,7 +130,8 @@ defined(CHIP_FAMILY_STM32H7) *reg &= ~mask; } -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) +#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) || \ + defined(CHIP_FAMILY_STM32H7) /* for families using a variable clock feeding the timer */ static void update_prescaler(void) { @@ -171,7 +172,7 @@ static void update_prescaler(void) #endif /* CONFIG_WATCHDOG_HELP */ } DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); -#endif /* defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) */ +#endif /* CHIP_FAMILY_STM32L || CHIP_FAMILY_STM32L4 || CHIP_FAMILY_STM32H7 */ int __hw_clock_source_init(uint32_t start_t) { |