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| author | Moritz Fischer <moritz.fischer@ettus.com> | 2019-02-27 11:34:02 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-16 01:53:35 -0700 |
| commit | 7b686a1f116d867c00516b6ceed91d5cb3e17398 (patch) | |
| tree | ac5758c84b331caba161c1b6df736b01e291dc13 /chip/stm32/hwtimer32.c | |
| parent | ed3b5e3a1fbf50c6e85e9e8e095b543fd6ebb78e (diff) | |
| download | chrome-ec-7b686a1f116d867c00516b6ceed91d5cb3e17398.tar.gz | |
chip: stm32: Fix Timers 9 through 11 for STM32F4
The timers 9 through 11 have different enable bits in the
STM32_RCC_APB2ENR on STM32F446/411/412 targets versus the
default (used by STM32F4/L4/STM32L) value set.
Break out the CHIP_FAMILY_STM32F4 case separately.
BRANCH=none
BUG=none
TEST=Observe PWM output on STM32412 EVM vs none before
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: I9f00902afe58ef8ef141da39b2b912ecc592944b
Reviewed-on: https://chromium-review.googlesource.com/1493273
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/hwtimer32.c')
| -rw-r--r-- | chip/stm32/hwtimer32.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index 683d5ff669..2faeb2f3b5 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -78,7 +78,7 @@ void __hw_timer_enable_clock(int n, int enable) reg = &STM32_RCC_APB2ENR; mask = STM32_RCC_PB2_TIM1; } -#elif defined(CHIP_FAMILY_STM32L) +#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) if (n >= 9 && n <= 11) { reg = &STM32_RCC_APB2ENR; mask = STM32_RCC_PB2_TIM9 << (n - 9); |