diff options
| author | Scott Collyer <scollyer@google.com> | 2020-05-02 15:49:54 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-29 03:49:21 +0000 |
| commit | ce168ae28c77a8b936efd2566dbf566834ba2913 (patch) | |
| tree | 25d98275f0037c8029e1daad5f020af1ea5df0ac /chip/stm32/hwtimer32.c | |
| parent | a78ca7b158c4ca6c33086b84b929a1c8385d8d09 (diff) | |
| download | chrome-ec-ce168ae28c77a8b936efd2566dbf566834ba2913.tar.gz | |
stm32g4: Add clock enable logic for HW timer
This CL adds clock enable support for stm32g4 family.
BUG=b:148493929
BRANCH=None
TEST=verfied that via scope that led toggle happens at 1 second window
when using one second hook call.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ie3d353ec40206e93cfac7b8738166ffee6c8442c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195548
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/stm32/hwtimer32.c')
| -rw-r--r-- | chip/stm32/hwtimer32.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index a2e6ab8f42..12057ad762 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -116,6 +116,17 @@ defined(CHIP_FAMILY_STM32H7) mask = STM32_RCC_PB2_TIM19; } #endif +#if defined(CHIP_FAMILY_STM32G4) + reg = &STM32_RCC_APB2ENR; + if (n == 1) + mask = STM32_RCC_APB2ENR_TIM1; + else if (n == 8) + mask = STM32_RCC_APB2ENR_TIM8; + else if (n == 20) + mask = STM32_RCC_APB2ENR_TIM20; + else if (n >= 15 && n <= 17) + mask = STM32_RCC_APB2ENR_TIM15 << (n - 15); +#endif if (n >= 2 && n <= 7) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM2 << (n - 2); |