diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2017-11-09 13:43:58 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-01-08 05:41:23 -0800 |
| commit | e24a3953c2c23df219fc0c735e0c188fd8edbded (patch) | |
| tree | d1b36505f04da9767ba75513287364f86f9b5eeb /chip/stm32/hwtimer32.c | |
| parent | 57bb4ddf4163dbe3da48ba56464adbabfa596344 (diff) | |
| download | chrome-ec-e24a3953c2c23df219fc0c735e0c188fd8edbded.tar.gz | |
stm32: Add STM32H7 family
Start adding support for the STM32H7 family of device and the first
available one the STM32H743.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=manual, run on stm32h743i-eval and zerblebarn boards
get a stable serial console.
Change-Id: I9ae10f0d843e5318451713c21ed22d455a23758c
Reviewed-on: https://chromium-review.googlesource.com/806168
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/stm32/hwtimer32.c')
| -rw-r--r-- | chip/stm32/hwtimer32.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index c3625955a5..c04f326770 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -73,7 +73,7 @@ void __hw_timer_enable_clock(int n, int enable) * Mapping of timers to reg/mask is split into a few different ranges, * some specific to individual chips. */ -#if defined(CHIP_FAMILY_STM32F0) +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7) if (n == 1) { reg = &STM32_RCC_APB2ENR; mask = STM32_RCC_PB2_TIM1; @@ -85,25 +85,28 @@ void __hw_timer_enable_clock(int n, int enable) } #endif -#if defined(CHIP_FAMILY_STM32F0) +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7) if (n >= 15 && n <= 17) { reg = &STM32_RCC_APB2ENR; mask = STM32_RCC_PB2_TIM15 << (n - 15); } #endif -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ +defined(CHIP_FAMILY_STM32H7) if (n == 14) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM14; } #endif -#if defined(CHIP_FAMILY_STM32F3) +#if defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32H7) if (n == 12 || n == 13) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM12 << (n - 12); } +#endif +#if defined(CHIP_FAMILY_STM32F3) if (n == 18) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM18; |