diff options
| author | Bossen WU <bossen.wu@stmicro.corp-partner.google.com> | 2021-05-18 17:21:56 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-30 08:36:48 +0000 |
| commit | 59b286058cf184e1dfc8b8332aa8adc811d8221d (patch) | |
| tree | caa7a17d679e52b6ed81de8eca011a7baccf7beb /chip/stm32/hwtimer32.c | |
| parent | 55f7cce1dcc9441979426fbe4226b3308a5df60e (diff) | |
| download | chrome-ec-59b286058cf184e1dfc8b8332aa8adc811d8221d.tar.gz | |
stm32: add stm32l431 ec in chip/stm32 : system / clock / timer
stm32l431 related driver: system / clock / timer.
The stm32l476g-eval is the only board which would be impacted.
BRANCH=main
BUG=b:188117811
TEST=make buildall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'chip/stm32/hwtimer32.c')
| -rw-r--r-- | chip/stm32/hwtimer32.c | 42 |
1 files changed, 37 insertions, 5 deletions
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index a643ccc134..963fa44e51 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -127,10 +127,22 @@ defined(CHIP_FAMILY_STM32H7) else if (n >= 15 && n <= 17) mask = STM32_RCC_APB2ENR_TIM15 << (n - 15); #endif +#if defined(CHIP_FAMILY_STM32L4) + if (n >= 2 && n <= 7) { + reg = &STM32_RCC_APB1ENR1; + mask = STM32_RCC_PB1_TIM2 << (n - 2); + } else if (n == 1 || n == 15 || n == 16) { + reg = &STM32_RCC_APB2ENR; + mask = (n == 1) ? STM32_RCC_APB2ENR_TIM1EN : + (n == 15) ? STM32_RCC_APB2ENR_TIM15EN : + STM32_RCC_APB2ENR_TIM16EN; + } +#else if (n >= 2 && n <= 7) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM2 << (n - 2); } +#endif if (!mask) return; @@ -258,6 +270,8 @@ const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) void hwtimer_setup_watchdog(void) { + int freq; + /* Enable clock */ __hw_timer_enable_clock(TIM_WATCHDOG, 1); /* Delay 1 APB clock cycle after the clock is enabled */ @@ -272,13 +286,31 @@ void hwtimer_setup_watchdog(void) STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000; STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000; - /* AUto-reload value */ - STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; + /* + * all timers has 16-bit prescale. + * For clock freq > 64MHz, 16bit prescale cannot meet 1KHz. + * set prescale as 10KHz and 10 times arr value instead. + * For clock freq < 64MHz, timer runs at 1KHz. + */ + freq = clock_get_timer_freq(); - /* Update prescaler: watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC) - 1; + if (freq <= 64000000 || !IS_ENABLED(CHIP_FAMILY_STM32L4)) { + /* AUto-reload value */ + STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; + + /* Update prescaler: watchdog timer runs at 1KHz */ + STM32_TIM_PSC(TIM_WATCHDOG) = + (freq / SECOND * MSEC) - 1; + } +#ifdef CHIP_FAMILY_STM32L4 + else { + /* 10 times ARR value with 10KHz timer */ + STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS * 10; + /* Update prescaler: watchdog timer runs at 10KHz */ + STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND / 10 * MSEC) - 1; + } +#endif /* Reload the pre-scaler */ STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001; |