Use 7bit I2C/SPI slave addresses in EC

Opt for 7bit slave addresses in EC code.  If 8bit is
expected by a driver, make it local and show this in
the naming.

Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase.  __7b indicates a
7bit address by itself.  __7bf indicates a 7bit address
with optional flags attached.  __8b indicates a 8bit
address by itself.

Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.

These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.

BUG=chromium:971296
BRANCH=none
TEST=make buildall -j

Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>

1 files changed, 10 insertions, 7 deletions

diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c
index 06836dd547..e263394880 100644
--- a/chip/stm32/i2c-stm32l4.c
+++ b/chip/stm32/i2c-stm32l4.c
@@ -26,7 +26,7 @@
 /* Transmit timeout in microseconds */
 #define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR__7BF
 #define I2C_SLAVE_ERROR_CODE	0xec
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
 #define IRQ_SLAVE STM32_IRQ_I2C1
@@ -177,7 +177,7 @@ static void i2c_init_port(const struct i2c_port_t *p)
 
 /*****************************************************************************/
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR__7BF
 
 static void i2c_event_handler(int port)
 {
@@ -303,9 +303,11 @@ DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_bytes,
+int chip_i2c_xfer__7bf(const int port, const uint16_t slave_addr__7bf,
+		  const uint8_t *out, int out_bytes,
 		  uint8_t *in, int in_bytes, int flags)
 {
+	int addr__8b = I2C_GET_ADDR__7b(slave_addr__7bf) << 1;
 	int rv = EC_SUCCESS;
 	int i;
 	int xfer_start = flags & I2C_XFER_START;
@@ -328,7 +330,7 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_bytes,
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
 		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| slave_addr
+			| addr__8b
 			| ((in_bytes == 0 && xfer_stop) ?
 				STM32_I2C_CR2_AUTOEND : 0)
 			| ((in_bytes == 0 && !xfer_stop) ?
@@ -357,7 +359,7 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_bytes,
 		 * set START bit to send (re)start and begin read transaction.
 		 */
 		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | slave_addr
+			| STM32_I2C_CR2_RD_WRN | addr__8b
 			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
 			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
 			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
@@ -451,11 +453,12 @@ static void i2c_init(void)
 	for (i = 0; i < i2c_ports_used; i++, p++)
 		i2c_init_port(p);
 
-#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR__7BF
 	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
 			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
 			| STM32_I2C_CR1_NACKIE;
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 | CONFIG_HOSTCMD_I2C_SLAVE_ADDR;
+	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
+		| (I2C_GET_ADDR__7b(CONFIG_HOSTCMD_I2C_SLAVE_ADDR__7BF) << 1);
 	task_enable_irq(IRQ_SLAVE);
 #endif
 }