diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-03-02 11:26:00 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-05 23:48:29 -0800 |
| commit | 63c849a363e119b75693760262644148d145dd01 (patch) | |
| tree | 545067be7a222ddb5c2e32b13ec651a5f1a4e999 /chip/stm32/memory_regions.inc | |
| parent | b42dd73603844c03b44d88a4513df330ee168496 (diff) | |
| download | chrome-ec-63c849a363e119b75693760262644148d145dd01.tar.gz | |
stm32: convert to CONFIG_CHIP_MEMORY_REGIONS
Remove the former special case for USB RAM
Add additional RAM regions for STM32H7.
For USB RAM, add an explicit alignment directive to ensure we always meet
the 8-byte boundary hardware constraint for the BTABLE.
This was already true because we put the .usb_ram.btable section first.
I keep this property by alpha-sorting the sections but makes it more
explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection,
99_lastsection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
TEST=build all targets with and without the patch and verify that all
smap files are identical.
Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175
Reviewed-on: https://chromium-review.googlesource.com/946369
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/memory_regions.inc')
| -rw-r--r-- | chip/stm32/memory_regions.inc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc new file mode 100644 index 0000000000..eaa9fc71f3 --- /dev/null +++ b/chip/stm32/memory_regions.inc @@ -0,0 +1,16 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifdef CONFIG_USB_RAM_SIZE +REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \ + CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2) +#endif /* CONFIG_USB_RAM_SIZE */ +#ifdef CHIP_VARIANT_STM32H7X3 +REGION(itcm, wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */ +REGION(dtcm, rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */ +REGION(ahb, rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */ +REGION(ahb4, rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */ +REGION(backup, rw, 0x38000000, 0x01000) /* Backup RAM: 4kB */ +#endif /* CHIP_VARIANT_STM32H7X3 */ |