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author | Randall Spangler <rspangler@chromium.org> | 2013-04-16 09:15:39 -0700 |
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committer | ChromeBot <chrome-bot@google.com> | 2013-04-16 14:55:12 -0700 |
commit | 9844e82ca8372ca71d973365b5fe7964b72c7f87 (patch) | |
tree | 9b210c5ac74a8b823c09d04e1dfa888d49f8efb8 /chip/stm32/power_led.c | |
parent | 357e508392ca37b60ea17a9ac5725f84586aac9e (diff) | |
download | chrome-ec-9844e82ca8372ca71d973365b5fe7964b72c7f87.tar.gz |
Remove _OFF from GPIO register macros
This is left over from when we had a pair of macros for each GPIO
register, one which concatenated its base address name and one which
took a base address. Only the latter has survived, but its naming is
longer than it needs to be and isn't consistent with other register
banks (USART, TIM, etc.).
No code changes, just renaming macros.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I15a282fd01db2a25219970e28ce551d8dc80193f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48226
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Diffstat (limited to 'chip/stm32/power_led.c')
-rw-r--r-- | chip/stm32/power_led.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c index 13568a254b..bad0c23d17 100644 --- a/chip/stm32/power_led.c +++ b/chip/stm32/power_led.c @@ -43,9 +43,9 @@ static void power_led_use_pwm(void) uint32_t val; /* Configure power LED GPIO for TIM2/PWM alternate function */ - val = STM32_GPIO_CRL_OFF(GPIO_B) & ~0x0000f000; + val = STM32_GPIO_CRL(GPIO_B) & ~0x0000f000; val |= 0x00009000; /* alt. function (TIM2/PWM) */ - STM32_GPIO_CRL_OFF(GPIO_B) = val; + STM32_GPIO_CRL(GPIO_B) = val; /* Enable TIM2 clock */ STM32_RCC_APB1ENR |= 0x1; |