diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2014-10-06 14:21:22 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-07 18:31:34 +0000 |
| commit | 7cde31850dfcfb6bfe8bfd94a09599c041b10409 (patch) | |
| tree | 3792117bec66e2695406e730ca8790a6bf8481f3 /chip/stm32/pwm.c | |
| parent | 7b305b752b6b22e48ce71160cc18b3ddcd0dfa89 (diff) | |
| download | chrome-ec-7cde31850dfcfb6bfe8bfd94a09599c041b10409.tar.gz | |
stm32: pwm: Fix duty cycle / frequency calculation
Correct frequency + duty cycle register calculations according to
datasheet.
BUG=chrome-os-partner:32089
TEST=Manual on Samus. Set 50% duty cycle and probe on scope, verify that
duty cycle is actually 50% and frequency is exactly 100 Hz.
BRANCH=samus.
Change-Id: I1e2c0bb7e53110367c38987b369fbef44af90a7d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221790
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'chip/stm32/pwm.c')
| -rw-r--r-- | chip/stm32/pwm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index 073e2df511..5b3ba75f8f 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -81,10 +81,10 @@ static void pwm_configure(enum pwm_channel ch) * ARR determines the wave period, CCRn determines duty cycle. * Thus, frequency = cpu_freq / PSC / ARR. so: * - * frequency = cpu_freq / (cpu_freq/10000) / 100 = 100 Hz. + * frequency = cpu_freq / (cpu_freq/10000 + 1) / (99 + 1) = 100 Hz. */ - tim->psc = clock_get_freq() / 10000; - tim->arr = 100; + tim->psc = clock_get_freq() / 10000 - 1; + tim->arr = 99; if (pwm->channel <= 2) /* Channel ID starts from 1 */ ccmr = &tim->ccmr1; |