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| author | Scott Collyer <scollyer@google.com> | 2020-08-25 13:54:58 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-31 23:27:33 +0000 |
| commit | 664002c97f1ff86f1ad4710c392051228b91d469 (patch) | |
| tree | 0436dffd615960bc758db741bca76172e3fab901 /chip/stm32/registers-stm32l4.h | |
| parent | 8dc68cd1c76cab0ac24f3d2d630f33c6de0317df (diff) | |
| download | chrome-ec-664002c97f1ff86f1ad4710c392051228b91d469.tar.gz | |
stm32l4: Refactor to use page instead of bank notation
The L4 and G4 family share the same flash peripheral block. Therefore,
the G4 can share the L4 driver. This CL adds macros which more closely
track the TRM description of the flash module, especially w.r.t
pages. There is no functional change for the L4 driver.
BUG=b:148493929
BRANCH=None
TEST=make -j BOARD=stm32l476g-eval is successful
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ie2c16ef2b8fa0e35f5945fb124765039f8ea22c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376388
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/registers-stm32l4.h')
| -rw-r--r-- | chip/stm32/registers-stm32l4.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h index e775dfe8a3..9fd6302f49 100644 --- a/chip/stm32/registers-stm32l4.h +++ b/chip/stm32/registers-stm32l4.h @@ -639,11 +639,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) #define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) #define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) -#define FLASH_WRP_START(val) ((val) & 0xff) -#define FLASH_WRP_END(val) (((val) >> 16) & 0xff) -#define FLASH_WRP_RANGE(strt, end) (((end) << 16) | (strt)) -#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(0xFF, 0x00) -#define FLASH_WRP_MASK FLASH_WRP_RANGE(0xFF, 0xFF) +/* Minimum number of bytes that can be written to flash */ +#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE #define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) #define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) |