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| author | Gwendal Grignou <gwendal@chromium.org> | 2017-07-20 10:15:40 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-07-28 17:45:13 -0700 |
| commit | a35218e20499a95ec7706f87cb48ff39c5451663 (patch) | |
| tree | e99e8d4d9d25b9f00d20cdf447da750397f14c7d /chip/stm32/registers.h | |
| parent | 1b25735b732e7766aceb3f060e4ca205aba6d358 (diff) | |
| download | chrome-ec-a35218e20499a95ec7706f87cb48ff39c5451663.tar.gz | |
stm32f4: Add OTP support.
Add support for OTP memory: if needed store serial number in first bank.
BUG=chromium:746471
BRANCH=none
TEST=On sweetberry, check we can write serial number with serialno
command. Check serial number survive a firmware update.
First, check without write protect, check we can write 0s (but not 1s)
serialno
Serial number: NNNNNNNNNNNNNNNNNNNNNN
>
> serial set MMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
After lock enabled, check we can not overwrite.
> serial set AMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
Access Denied
Check that serialno returns "Uninitialized" if it was never set.
Change-Id: I9ab08486a7c3e1958e964649640d69b5b70947e3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580290
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 764dc79af6..3e1bf1df14 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1479,6 +1479,19 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_OPTB_COMPL_SHIFT 8 +#define STM32_OTP_BASE 0x1FFF7800 +#define STM32_OTP_BLOCK_NB 16 +#define STM32_OTP_BLOCK_SIZE 32 +#define STM32_OTP_BLOCK_DATA(_block, _offset) \ + (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) +#define STM32_OTP_UNLOCK_BYTE 0x00 +#define STM32_OTP_LOCK_BYTE 0xFF +#define STM32_OTP_LOCK_BASE \ + (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) +#define STM32_OTP_LOCK(_block) \ + (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) +#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) + #else #error Unsupported chip variant #endif |