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| author | Gwendal Grignou <gwendal@chromium.org> | 2015-07-25 02:49:00 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-30 19:58:09 +0000 |
| commit | ff550b0e1abfc97a8531eed5515c75e0f37deba3 (patch) | |
| tree | 9a9148a436f719437996d4703e2198942b9b5b3d /chip/stm32/registers.h | |
| parent | a3a5c90b54670ddc865defc16757f1fef78ca322 (diff) | |
| download | chrome-ec-ff550b0e1abfc97a8531eed5515c75e0f37deba3.tar.gz | |
stm32: Enable 3rd SPI interface
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 4970ea5f4b..f9f27f25f5 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -605,6 +605,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_PB1_WWDG (1 << 11) #define STM32_RCC_PB1_IWDG (1 << 12) /* DBGMCU only */ #define STM32_RCC_PB1_SPI2 (1 << 14) +#define STM32_RCC_PB1_SPI3 (1 << 15) #define STM32_RCC_PB1_USART2 (1 << 17) #define STM32_RCC_PB1_USART3 (1 << 18) #define STM32_RCC_PB1_USART4 (1 << 19) @@ -681,9 +682,6 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_SPI2_BASE 0x40003800 #define STM32_SPI3_BASE 0x40003c00 /* STM32F373 */ -#define STM32_SPI1_PORT 0 -#define STM32_SPI2_PORT 1 - /* The SPI controller registers */ struct stm32_spi_regs { uint16_t cr1; @@ -705,6 +703,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) #define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) +#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI_CR1_BIDIMODE (1 << 15) #define STM32_SPI_CR1_BIDIOE (1 << 14) @@ -1160,6 +1159,8 @@ enum dma_channel { #ifdef CHIP_VARIANT_STM32F373 STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, + STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, + STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, STM32_DMAC_COUNT = 10, #else |