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| author | Vic (Chun-Ju) Yang <victoryang@chromium.org> | 2014-04-22 10:05:48 +0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-04-30 09:49:01 +0000 |
| commit | 1b7573c3e9484b35ee62c1160719076e8e9d8837 (patch) | |
| tree | 29fc82e326c65ddadebc9c41dc9dcea9962b3bb0 /chip/stm32/registers.h | |
| parent | 39588b067fe2411a326fcec23a5df6584f20fab7 (diff) | |
| download | chrome-ec-1b7573c3e9484b35ee62c1160719076e8e9d8837.tar.gz | |
Keyborg: implement matrix scanning
This implements dual chip matrix scanning. Now the scan result is only
dumped to debug output.
BUG=None
TEST=Put a finger on the panel and see its shape.
BRANCH=None
Change-Id: I015c901b42e24fe4a6249c12c37bc5bfcb308c9f
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196468
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index c6b2acef09..3741a38c69 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1166,6 +1166,29 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_CRC_CR_REV_IN_WORD (3 << 5) #define STM32_CRC_CR_REV_OUT (1 << 7) +/* --- PMSE --- */ +#define STM32_PMSE_BASE 0x40013400 + +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) + /* --- MISC --- */ #define STM32_CEC_BASE 0x40007800 /* STM32F100 only */ |