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| author | Vic Yang <victoryang@chromium.org> | 2013-08-29 16:42:02 +0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-09-05 03:10:09 +0000 |
| commit | b57a5fe0edfcd8fa264c2f83755f5c6ae73d8435 (patch) | |
| tree | 23d2690e7261d82277ae179a56a60070c3591f0b /chip/stm32/registers.h | |
| parent | c34d0cc8bf4308046d2d213f4ff744b011e0edbe (diff) | |
| download | chrome-ec-b57a5fe0edfcd8fa264c2f83755f5c6ae73d8435.tar.gz | |
STM32L ADC driver
ADC module on STM32L is clocked by HSI oscillator, and thus we need to
switch to HSI if using MSI. After the conversion, if the system is not
in S0, clock is switched back to MSI again.
There are several register bits that can only be written when ADC is
powered down. For now, let's just power down the ADC after each
conversion.
Currently ADC watchdog is not working and is disabled on STM32L.
BUG=chrome-os-partner:22242
TEST=Try multiple all-channel and single-channel reads in S0 and S5.
BRANCH=None
Change-Id: I769dda8a9c69ac9de1eb22d6d259034eef8c1ac4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167454
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 2d75a0d249..bb8dcb21e2 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -605,12 +605,42 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) #define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) #define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) #define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) #define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) #define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) #define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) #define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) #define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#elif defined(CHIP_FAMILY_stm32l) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) +#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) +#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) +#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) +#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) +#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) +#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) +#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) + +#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) #endif /* --- DMA --- */ |