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| author | Randall Spangler <rspangler@chromium.org> | 2013-05-17 13:12:01 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-05-22 19:15:56 -0700 |
| commit | e8ecda5e8d0384ddc8fe6b3bd9e991ee6d84faae (patch) | |
| tree | 402184e035d6e792ccfa41fbdf4caf9b9c8abece /chip/stm32/registers.h | |
| parent | 6592036c6c6b24744ac3bb1450ee41f0c7630b10 (diff) | |
| download | chrome-ec-e8ecda5e8d0384ddc8fe6b3bd9e991ee6d84faae.tar.gz | |
Support flash write protect on STM32L
This adds support for write protecting the RO code at boot, and the
entire flash on demand.
Implementation if WP# is not asserted is currently a little different
than STM32F and LM4; RO is still protected at boot if ro_at_boot, but
can be unprotected and the change will commit on the next reboot.
This saves the bank of flash which we use for pstate on LM4 and
STM32F. I think I can use one of the unused option bits (WRP2 bit 0)
to hold the RO-at-boot flag, in which case I can more closely match
the behavior of the other chips, but I'd like to do that (or give up
and implement pstate) in a separate CL so it's clearer what I'm doing.
BUG=chrome-os-partner:15613
BRANCH=none
TEST=manual
- flashinfo -> (no flags)
- enable WP (via screw or dut-control)
- flashinfo -> wp_gpio_asserted
- flashwp enable
- flashinfo -> wp_gpio_asserted ro_at_boot
- flashwp now
- flashinfo -> wp_gpio_asserted ro_at_boot all_now
- flashwp disable -> fails
- flashinfo -> wp_gpio_asserted ro_at_boot all_now
- flasherase 0x1fc00 0x400 -> fails
- reboot
- flashinfo -> wp_gpio_asserted ro_at_boot ro_now
- flasherase 0xfc00 0x400 -> fails
- flasherase 0x1fc00 0x400 -> succeeds
- disable WP (via screw or dut-control)
- reboot
- flashinfo -> ro_at_boot ro_now
- flashwp disable
- flashinfo -> ro_now
- reboot
- flashinfo -> (no flags)
- flasherase 0xfc00 0x400 -> succeeds
- flasherase 0x1fc00 0x400 -> succeeds
Change-Id: Id1b6b099a44a1985a5ab9387feb882a8f26e3aa1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/55594
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 2edc9d2fb2..148d1f2e08 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -475,10 +475,23 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_PECR_PE_LOCK (1 << 0) +#define STM32_FLASH_PECR_PRG_LOCK (1 << 1) +#define STM32_FLASH_PECR_OPT_LOCK (1 << 2) +#define STM32_FLASH_PECR_PROG (1 << 3) +#define STM32_FLASH_PECR_ERASE (1 << 9) +#define STM32_FLASH_PECR_FPRG (1 << 10) +#define STM32_FLASH_PECR_OBL_LAUNCH (1 << 18) #define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) #define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF +#define STM32_FLASH_PEKEYR_KEY2 0x02030405 #define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF +#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 #define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 +#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 #define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) #define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) #define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) @@ -487,6 +500,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_OPTB_RDP_OFF 0x00 #define STM32_OPTB_USER_OFF 0x04 +#define STM32_OPTB_WRP01 0x08 #define STM32_OPTB_WRP_OFF(n) (0x08 + (n&1) + (n&2) * 2) #define STM32_OPTB_WRP23 0x0c |