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| author | Vincent Palatin <vpalatin@chromium.org> | 2017-03-21 15:29:11 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-03-24 19:38:04 -0700 |
| commit | d8cbf0dc402619cc7e027534c196abd9059ab98a (patch) | |
| tree | 1b3b29de134a0cb6970824a7664b4d385f480af8 /chip/stm32/registers.h | |
| parent | d9afaba9b4043a9d953b0d4c4e846520b04a0597 (diff) | |
| download | chrome-ec-d8cbf0dc402619cc7e027534c196abd9059ab98a.tar.gz | |
stm32: add internal flash support for STM32L4 family
Add a flash driver for the STM32L4 family.
For write and erase, the code is very similar to other variants
excepted the 'normal' writes need to be perform 2 aligned
32-bit words at a time.
Option bytes are a sligthly easier business since the hardware deals
with the option bytes page preserving and erasing for us.
For the write-protection, the STM32L4 is slightly different from the
other variants. The write-protection granularity is still a 2-kB block
(2kB here) but instead of having a 'bitmap' of the protected blocks, it
defines 2 write-protection ranges (WRP1AR and WRP1BR).
For the EC code base, we are using WRP1AR to protect the Read-Only
regions and WRP1BR to protect the Rollback and RW regions (if they
exist).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35648258
TEST=On Eve, run 'flashrom -p ec:type=fp -w /tmp/ec.bin'
and 'flashrom -p ec:type=fp --wp-enable --wp-range 0x0 0x20000'
Change-Id: Iaa98c1b4d3b07de2923ac076624bd4601c31a600
Reviewed-on: https://chromium-review.googlesource.com/456711
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index a8104114cf..f0bd1cf861 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1323,30 +1323,41 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_FLASH_ACR_DCEN (1 << 10) #define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) #define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB #define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F #define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) #define FLASH_SR_BUSY (1 << 16) -#define FLASH_SR_ERR_MASK (0xc3fb) +#define FLASH_SR_ERR_MASK (0xc3fa) #define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) #define FLASH_CR_PG (1 << 0) #define FLASH_CR_PER (1 << 1) #define FLASH_CR_STRT (1 << 16) +#define FLASH_CR_OPTSTRT (1 << 17) +#define FLASH_CR_OBL_LAUNCH (1 << 27) +#define FLASH_CR_OPTLOCK (1 << 30) #define FLASH_CR_LOCK (1 << 31) #define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_SNB(0xff) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) #define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) #define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) #define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) #define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) #define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) #define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) +#define FLASH_WRP_START(val) ((val) & 0xff) +#define FLASH_WRP_END(val) (((val) >> 16) & 0xff) +#define FLASH_WRP_RANGE(strt, end) (((end) << 16) | (strt)) +#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(0xFF, 0x00) +#define FLASH_WRP_MASK FLASH_WRP_RANGE(0xFF, 0xFF) #define STM32_OPTB_BASE 0x1FFF7800 -#define STM32_OPTB_USER_RDP_OFF 0x00 -#define STM32_OPTB_WRP1A 0x18 -#define STM32_OPTB_WRP1B 0x20 -#define STM32_OPTB_COMPL_OFF 4 +#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) +#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) #elif defined(CHIP_FAMILY_STM32F4) #define STM32_FLASH_REGS_BASE 0x40023c00 |