diff options
| author | Philip Chen <philipchen@google.com> | 2017-09-22 14:29:40 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-11 13:19:33 -0700 |
| commit | 982f2bbfab02400cb09b7d7102db3285c1723762 (patch) | |
| tree | 1d7e9b38c83b7a54710c61028df3dcaf70a5791d /chip/stm32/registers.h | |
| parent | df12bc1c0246ceec39f28151efadb73f8e5fd7a5 (diff) | |
| download | chrome-ec-982f2bbfab02400cb09b7d7102db3285c1723762.tar.gz | |
chip/stm32/clock: Optionally use LSE as RTCCLK
The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz.
To use stm32 RTC for applications requiring accurate timing, let's setup
LSE (a more accurate clock source) as RTCCLK.
Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally.
BUG=b:63908519
BRANCH=none
TEST=boot scarlet rev1 and wait for an hour,
confirm rtc time == kernel system time.
Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/679601
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index bfe5b7321c..491718f631 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1109,11 +1109,6 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) #define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_BDCR_BDRST (1 << 16) -#define STM32_RCC_BDCR_RTCEN (1 << 15) -#define BCDR_RTCSEL(source) (((source) & 0x3) << 8) -#define BDCR_SRC_HSE 0x3 -#define BDCR_SRC_LSI 0x2 #define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) #define STM32_RCC_CSR_LSION (1 << 0) #define STM32_RCC_CSR_LSIRDY (1 << 1) @@ -1141,6 +1136,17 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #error Unsupported chip variant #endif +/* RTC domain control register */ +#define STM32_RCC_BDCR_BDRST (1 << 16) +#define STM32_RCC_BDCR_RTCEN (1 << 15) +#define STM32_RCC_BDCR_LSERDY (1 << 1) +#define STM32_RCC_BDCR_LSEON (1 << 0) +#define BDCR_RTCSEL_MASK ((0x3) << 8) +#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) +#define BDCR_SRC_LSE 0x1 +#define BDCR_SRC_LSI 0x2 +#define BDCR_SRC_HSE 0x3 + /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ #define STM32_RCC_PB1_TIM2 (1 << 0) #define STM32_RCC_PB1_TIM3 (1 << 1) |